Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder

In this thesis, we present an FPGA implementation of parallel-node low-density-parity-check convolutional-code (PN-LDPC-CC) encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) PN-LDPC-CC encoder and decoder were implemented on an Altera development and education board (DE4). Detailed power measurements of the FPGA board for various configurations of the design have been conducted to characterize the power consumption of the decoder module. For an Eb/N0 of 5 dB, the decoder with 9 processor cores (pipelined decoder iteration stages) has a bit-error-rate performance of 10E-10 and achieves an energy-per-coded-bit of 1.683 nJ based on raw power measurement results. The increase in Eb/N0 can effectively reduce the decoder power and energy-per-coded-bit for configurations with 5 or more processor cores for Eb/N0 < 5 dB. The incremental decoder power cost and incremental energy-per-coded-bit also hold a linearly decreasing trend for each additional processor core. Additional experiments are performed to account for the effect of the efficiency of the DC/DC converter circuitry on the raw power measurement data. Further experiments have also been conducted to quantify the effect of clipping thresholds, bit width for each processor core on bit-error-rate (BER) performance, power consumption, and logic utilization of the decoder. A “6Core" decoder with growing bit-width log-likelihood ratios (LLRs) has been found to have a BER performance near that of a “6Core" 6-bit decoder while consuming similar power, and logic utilization to that of a 5-bit “6Core" decoder

Field Oriented Sliding Mode Control of Surface-Mounted Permanent Magnet AC Motors: Theory and Applications to Electrified Vehicles

Permanent magnet ac motors have been extensively utilized for adjustable-speed traction motor drives, due to their inherent advantages including higher power density, superior efficiency and reliability, more precise and rapid torque control, larger power factor, longer bearing, and insulation life-time. Without any proportional-and-integral (PI) controllers, this paper introduces novel first- and higher-order field-oriented sliding mode control schemes. Compared with the traditional PI-based vector control techniques, it is shown that the proposed field oriented sliding mode control methods improve the dynamic torque and speed response, and enhance the robustness to parameter variations, modeling uncertainties, and external load perturbations. While both first- and higher-order controllers display excellent performance, computer simulations show that the higher-order field-oriented sliding mode scheme offers better performance by reducing the chattering phenomenon, which is presented in the first-order scheme. The higher-order field-oriented sliding mode controller, based on the hierarchical use of supertwisting algorithm, is then implemented with a Texas Instruments TMS320F28335 DSP hardware platform to prototype the surface-mounted permanent magnet ac motor drive. Last, computer simulation studies demonstrate that the proposed field-oriented sliding mode control approach is able to effectively meet the speed and torque requirements of a heavy-duty electrified vehicle during the EPA urban driving schedule

Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

National Educators' Workshop. Update 92: Standard Experiments in Engineering Materials Science and Technology

This document contains a collection of experiments presented and demonstrated at the workshop. The experiments related to the nature and properties of engineering materials and provided information to assist in teaching about materials in the education community

Measurements, Models, Systems and Design

531 s.

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

Energy: A continuing bibliography with indexes, issue 31

This bibliography lists 1111 reports, articles, and other documents introduced into the NASA scientific and technical information system from July 1, 1981 through September 30, 1981

FLEXIBLE LOW-COST HW/SW ARCHITECTURES FOR TEST, CALIBRATION AND CONDITIONING OF MEMS SENSOR SYSTEMS

During the last years smart sensors based on Micro-Electro-Mechanical systems (MEMS) are widely spreading over various fields as automotive, biomedical, optical and consumer, and nowadays they represent the outstanding state of the art. The reasons of their diffusion is related to the capability to measure physical and chemical information using miniaturized components. The developing of this kind of architectures, due to the heterogeneities of their components, requires a very complex design flow, due to the utilization of both mechanical parts typical of the MEMS sensor and electronic components for the interfacing and the conditioning. In these kind of systems testing activities gain a considerable importance, and they concern various phases of the life-cycle of a MEMS based system. Indeed, since the design phase of the sensor, the validation of the design by the extraction of characteristic parameters is important, because they are necessary to design the sensor interface circuit. Moreover, this kind of architecture requires techniques for the calibration and the evaluation of the whole system in addition to the traditional methods for the testing of the control circuitry. The first part of this research work addresses the testing optimization by the developing of different hardware/software architecture for the different testing stages of the developing flow of a MEMS based system. A flexible and low-cost platform for the characterization and the prototyping of MEMS sensors has been developed in order to provide an environment that allows also to support the design of the sensor interface. To reduce the reengineering time requested during the verification testing a universal client-server architecture has been designed to provide a unique framework to test different kind of devices, using different development environment and programming languages. Because the use of ATE during the engineering phase of the calibration algorithm is expensive in terms of ATE’s occupation time, since it requires the interruption of the production process, a flexible and easily adaptable low-cost hardware/software architecture for the calibration and the evaluation of the performance has been developed in order to allow the developing of the calibration algorithm in a user-friendly environment that permits also to realize a small and medium volume production. The second part of the research work deals with a topic that is becoming ever more important in the field of applications for MEMS sensors, and concerns the capability to combine information extracted from different typologies of sensors (typically accelerometers, gyroscopes and magnetometers) to obtain more complex information. In this context two different algorithm for the sensor fusion has been analyzed and developed: the first one is a fully software algorithm that has been used as a means to estimate how much the errors in MEMS sensor data affect the estimation of the parameter computed using a sensor fusion algorithm; the second one, instead, is a sensor fusion algorithm based on a simplified Kalman filter. Starting from this algorithm, a bit-true model in Mathworks Simulink(TM) has been created as a system study for the implementation of the algorithm on chip

Development of a portable time-domain system for diffuse optical tomography of the newborn infant brain

Conditions such as hypoxic-ischaemic encephalopathy (HIE) and perinatal arterial ischaemic stroke (PAIS) are causes of lifelong neurodisability in a few hundred infants born in the UK each year. Early diagnosis and treatment are key, but no effective bedside detection and monitoring technology is available. Non-invasive, near-infrared techniques have been explored for several decades, but progress has been inhibited by the lack of a portable technology, and intensity measurements, which are strongly sensitive to uncertain and variable coupling of light sources and detector to the scalp. A technique known as time domain diffuse optical tomography (TD-DOT) uses measurements of photon flight times between sources and detectors placed on the scalp. Mean flight time is largely insensitive to the coupling and variation in mean flight time can reveal spatial variation in blood volume and oxygenation in regions of brain sampled by the measurements. While the cost, size and high power consumption of such technology have hitherto prevented development of a portable imaging system, recent advances in silicon technology are enabling portable and low-power TD-DOT devices to be built. A prototype TD-DOT system is proposed and demonstrated, with the long-term aim to design a portable system based on independent modules, each supporting a time-of-flight detector and a pulsed source. The operation is demonstrated of components that can be integrated in a portable system: silicon photodetectors, integrated circuit-based signal conditioning and time detection -- built using a combination of off-the-shelf components and reconfigurable hardware, standard computer interfaces, and data acquisition and calibration software. The only external elements are a PC and a pulsed laser source. This thesis describes the design process, and results are reported on the performance of a 2-channel system with online histogram generation, used for phantom imaging. Possible future development of the hardware is also discussed