A High-speed and Low Power Electrical Link Transceiver

On-chip wires will present increasing latency and energy problems as VLSI technologies continue to scale. Interconnects have an RC-limited bandwidth approximately proportional to the area of the metal cross section and inversely proportional to the squared length. To overcome RC-limited channels, an energy-efficient on-chip transceiver is presented that contains a hybrid transmitter, a current-sense receiver, and self-testing blocks. The main goal of this research is having a relatively low-power transceiver, which can be used as an on-chip communication system. By adding a pre-emphasis circuit in the transmitter, pre-cursor inter-symbol interference can be canceled. A hybrid transmitter which combines voltage-mode pre-emphasis with a current-mode main driver is used. This structure can save pre-emphasis current, and leads to reduced power dissipation especially in the static situation. A current-sense amplifier is implemented with a cross-coupled stage and an active inductor equalizer at the receiver, in order to boost the data rate while maintaining good energy efficiency. An offset cancelation circuit is incorporated to make a robust comparator for the receiver. According to simulation results, the transceiver has low power consumption with 1.2 V, 130 nm CMOS technology. The performance shows that it operates at 8 Gb/s over a 5 mm and 19 dB loss differential channel. The overall dynamic power consumption is 2.05 mW, without the PRBS generator/checker. Therefore, this transceiver has high data rate and low power consumption

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects

Silicon-organic hybrid electro-optic modulators for high-speed communication systems

Der Austausch von Informationen über globale Kommunikationsnetze ist für viele alltägliche Lebensbereiche selbstverständlich geworden. Die Informationen werden dabei mit immer weiter wachsender Geschwindigkeit und in zunehmendem Umfang geteilt. Durch den enormen Anstieg des Datenverkehrs kommt verstärkt optische Nachrichtentechnik zum Einsatz. Sie bietet gegenüber elektronischen Übertragungsverfahren entscheidende Vorteile bezüglich der Übertragungsdistanz und -kapazität.Wurde optische Übertragung zunächst nur für die Kommunikation über weite Strecken eingesetzt, machen sich die Nachteile elektronischer Verfahren mit dem stark anwachsenden Datenverkehr auch zunehmend über kürzere Strecken bemerkbar, sodass auch dort vermehrt optische Kommunikationssysteme zum Einsatz kommen. Insgesamt nimmt die Anzahl der photonischen Komponenten, die in Kommunikationsanwendungen eingesetzt werden, dadurch rapide zu. Dies führt dazu, dass die einzelnen Bauteile kostengünstiger, energieeffizienter sowie kompakter werden müssen. Ähnlich zur Entwicklung in der Mikroelektronik, wo immer stärkere Miniaturisierung zu einer dramatischen Leistungssteigerung bei gleichzeitiger Reduktion von Kosten, Platzbedarf und Energieverbrauch geführt hat, soll dies in der Photonik durch die Anwendung von integrierten photonischen Schaltkreisen erreicht werden. Integrierte photonische Schaltkreise zeichnen sich durch hohe Funktionalität bei geringem Platzbedarf aus und ermöglichen eine kostengünstige Massenfertigung. Sie sind daher von erheblichem wissenschaftlichen, technischen und kommerziellen Interesse. Insbesondere die Integration auf Siliziumsubstraten verspricht dabei hohe Integrationsdichten, kombiniert mit der Möglichkeit zur Ko-Integration photonischer und elektronischer Schaltkreise. Ein entscheidender Vorteil ist dabei, dass Silizium seit Jahrzehnten das dominierende Material in der Halbleiterindustrie und eines der häufigsten Elemente der Erdkruste ist. Vorteilhaft ist also neben der guten Verfügbarkeit des Materials, insbesondere die Existenz von etablierten und zuverlässigen Prozessen aus der Mikroelektronik, speziell der CMOS-Fertigung, zur lithographischen Strukturierung. Zudem bietet Silizium viele für die integrierte Photonik günstige physikalische Eigenschaften. Beispielsweise die Transparenz im für die Datenübertragung technisch relevanten Spektralbereiche im Nahinfraroten zwischen 1260 nm und 1625 nm und einen hohen Brechungsindexkontrast zu Siliziumdioxid. Die unter dem Begriff Siliziumphotonik zusammengefasste Technologie ist daher eine vielversprechende Plattform für integrierte photonische Schaltkreise. Eines der wichtigsten Bauteile in der optischen Nachrichtentechnik ist der elektro-optische (EO) Modulator. An der Schnittstelle zwischen Elektronik und Optik ist er das zentrale Element in optischen Sendern. Neben geringen Herstellungskosten, geringem Platzbedarf und guter Energieeffizienz ist eine hohe Modulationsgeschwindigkeit eine essentielle Fähigkeit des Modulators, da diese hohe Bandbreiten in der Datenübertragung ermöglicht. Da Silizium aufgrund der punktsymmetrischen Kristallstruktur keine optische Nichtlinearität zweiter Ordnung aufweist, ist in reinem Silizium kein linearer EO Effekt (Pockels-Effekt) verfügbar. Elektro-optische Modulatoren aus Silizium basieren daher darauf, dass die Konzentration freier Ladungsträger in einem Siliziumwellenleiter moduliert wird, was beispielsweise durch Anlegen einer Spannung an einen pn-Übergang realisiert werden kann. Die Änderung der Konzentration freier Ladungsträger führt dabei zu einer Variation des optischen Brechungsindex (Plasmadispersions-Effekt). Dieser Effekt ist jedoch nicht effizient,wodurch die Energieeffizienz reiner Siliziummodulatoren insgesamt limitiert ist. Durch die heterogene Integration von Silizium mit weiteren Materialien lässt sich die Siliziumphotonik-Plattform erweitern. Organische EO Materialien lassen sich durch molekulares Design gezielt auf einen starken linearen EO Effekt hin optimieren. Durch die Kombination von Silizium-Nanowellenleitern und organischen EO Materialien lassen sich Hybridbauteile realisieren, welche wesentlich energieeffizienter als reine Siliziummodulatoren sind. In der englischsprachigen Fachliteratur werden diese Bauteile auch als silicon-organic hybrid (SOH) bezeichnet. Die vorliegende Arbeit befasst sich mit SOH-Modulatoren und deren praktischer Anwendung in der optischen Hochgeschwindigkeitskommunikation. In vorausgehenden Arbeiten wurden die fundamentalen Prinzipien von SOHModulatoren untersucht und deren grundlegende Einsetzbarkeit für die optische Datenübertragung gezeigt. Die vorliegende Arbeit baut darauf auf und adressiert gezielt Aspekte, die für einen praktischen Einsatz von SOH Bauteilen in optischen Kommunikationssystemen von großer Bedeutung sind: Um ein zielgerichtetes Design der Bauteile zu ermöglichen und grundlegende Zielkonflikte im Design zu erkennen, wird ein Modell für das dynamische EO Verhalten der Modulatoren entwickelt und experimentell verifiziert. Für die breitbandige Aufbau- und Verbindungstechnik werden Konzepte zur elektrischen Anbindung schneller SOH-Modulatoren entwickelt und demonstriert. Verschiedene Modulationsformate werden bei Bruttodatenraten von bis zu 160 Gbit/s erfolgreich getestet und demonstrieren die Eignung von SOHModulatoren für praktische Anwendungsszenarien. Kapitel 1 gibt eine kurze Einführung in das Gebiet der Siliziumphotonik und deren Bedeutung für die optische Datenübertragung. Kapitel 2 beschreibt die theoretischen und technologischen Grundlagen elektrooptischer Bauteile auf Basis der Siliziumphotonik. Dies umfasst einen Überblick über den zugehörigen Stand der Wissenschaft und Technik sowie die für die nachfolgenden Kapitel relevanten Konzepte aus der Hochfrequenz- und der Nachrichtentechnik. Kapitel 3 führt ein quantitatives Modell zur Beschreibung der dynamischen elektrischen und EO Eigenschaften von SOH-Modulatoren ein. Das Modell wird experimentell verifiziert und dient als Grundlage für verbesserte Bauteildesigns zukünftiger SOH-Modulatoren, mit denen sich Bandbreiten von mehr als 100 GHz und $\pi$-Spannungen von unter 1 V erreichen lassen. Kapitel 4 demonstriert die Eignung von SOH-Modulatoren für technisch relevante Intensitätsmodulation/Direktempfang-Verfahren (engl. intensity modulation/direct detection, IM/DD), die insbesondere für hochgradig skalierbare Übertragungssysteme mit kleinen und mittleren Reichweiten (board-to-board, rack-to-rack) interessant sind. In diesem Zusammenhang werden verschiedene IM/DD-Modulationsformate experimentell getestet und dabei Bruttodatenraten von bis zu 120 Gbit/s demonstriert. Kapitel 5 befasst sich mit der elektrischen Aufbau- und Verbindungstechnik für SOH-Modulatoren. Dies erfordert Platinen mit guten Hochfrequenzeigenschaften und kleinen Strukturgrößen, um eine hohe Integrationsdichte zu erreichen. Ein Verfahren zur Herstellung von hochfrequenztechnisch breitbandigen Keramikplatinen mit hoher räumlicher Auflösung wird vorgestellt. Mit Hilfe dieser Keramikplatinen wird ein mit Bonddrähten elektrisch angebundener SOH-Modulator vorgestellt und damit eine Bruttodatenrate von 160 Gbit/s demonstriert. Kapitel 6 fasst die vorliegende Arbeit zusammen und gibt einen Ausblick auf zukünftig notwendige Schritte, um die Anwendungsreife von SOH-Modulatoren zu erreichen. Zudem werden potentielle weitere Anwendungsfelder für SOH-Modulatoren diskutiert

Design of Low-Power NRZ/PAM-4 Wireline Transmitters

Rapid growing demand for instant multimedia access in a myriad of digital devices has pushed the need for higher bandwidth in modern communication hardwares ranging from short-reach (SR) memory/storage interfaces to long-reach (LR) data center Ethernets. At the same time, comprehensive design optimization of link system that meets the energy-efficiency is required for mobile computing and low operational cost at datacenters. This doctoral study consists of design of two low-swing wireline transmitters featuring a low-power clock distribution and 2-tap equalization in energy-efficient manners up to 20-Gb/s operation. In spite of the reduced signaling power in the voltage-mode (VM) transmit driver, the presence of the segment selection logic still diminishes the power saving benefit. The first work presents a scalable VM transmitter which offers low static power dissipation and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating driver segmentation and reducing pre-driver complexity and dynamic power. Per-channel quadrature clock generation with injection-locked oscillators (ILO) allows the generation of rail-to-rail quadrature clocks. Energy efficiency is further improved with capacitively driven low-swing global clock distribution and supply scaling at lower data rates, while output eye quality is maintained at low voltages with automatic phase calibration of the local ILO-generated quarter-rate clocks. A prototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock distribution network and two transmitters that support an output swing range of 100-300mV with up to 12-dB of equalization. The transmitters achieve 8-16 Gb/s operation at 0.65-1.05 pJ/b energy efficiency. The second work involves a dual-mode NRZ/PAM-4 differential low-swing voltage-mode (VM) transmitter. The pulse-selected output multiplexing allows reduction of power supply and deterministic jitter caused by large on-chip parasitic inherent in the transmission-gate-based multiplexers in the earlier work. Analog impedance control replica circuits running in the background produce gate-biasing voltages that control the peaking ratio for 2-tap feed-forward equalization and PAM-4 symbol levels for high-linearity. This analog control also allows for efficient generation of the middle levels in PAM-4 operation with good linearity quantified by level separation mismatch ratio of 95%. In NRZ mode, 2-tap feedforward equalization is configurable in high-performance controlled-impedance or energy-efficient impedance-modulated settings to provide performance scalability. Analytic design consideration on dynamic power, data-rate, mismatch, and output swing brings optimal performance metric on the given technology node. The proof-of-concept prototype is verified on silicon with 65 nm CMOS process with improved performance in speed and energy-efficiency owing to double-stack NMOS transistors in the output stage. The transmitter consumes as low as 29.6mW in 20-Gb/s NRZ and 25.5mW in the 28-Gb/s PAM-4 operations

Transmetteurs photoniques sur silicium pour les transmissions optiques à grande capacité

Les applications exigeant des très nombreuses données (médias sociaux, diffusion vidéo en continu, mégadonnées, etc.) se développent à un rythme rapide, ce qui nécessite de plus en plus de liaisons optiques ultra-rapides. Ceci implique le développment des transmetteurs optiques intégrés et à bas coût et plus particulirement en photonique sur silicium en raison de ses avantages par rapport aux autres technologies (LiNbO3 et InP), tel que la compatibilité avec le procédé de fabrication CMOS. Les modulateurs optoélectronique sont un élément essentiel dans la communication op-tique. Beaucoup de travaux de recherche sont consacrées au développement de dispositifs optiques haut débit efficaces. Cependant, la conception de modulateurs en photonique sur sili-cium (SiP) haut débit est diffcile, principalement en raison de l'absence d'effet électro-optique intrinsèque dans le silicium. De nouvelles approches et de architectures plus performances doivent être développées afin de satisfaire aux critères réliés au système d'une liaison optique aux paramètres de conception au niveau du dispositif integré. En outre, la co-conception de circuits integrés photoniques sur silicium et CMOS est cruciale pour atteindre tout le potentiel de la technologie de photonique sur silicium. Ainsi cette thèse aborde les défits susmentionnés. Dans notre première contribution, nous préesentons pour la première fois un émetteur phononique sur silicium PAM-4 sans utiliser un convertisseur numérique analog (DAC)qui comprend un modulateur Mach Zehnder à électrodes segmentées SiP (LES-MZM) implémenté dans un procédé photonique sur silicium générique avec jonction PN latérale et son conducteur CMOS intégré. Des débits allant jusqu'à 38 Gb/s/chnnel sont obtenus sans utili-ser un convertisseur numérique-analogique externe. Nous présentons également une nouvelle procédure de génération de délai dans le excitateur de MOS complémentaire. Un effet, un délai robuste aussi petit que 7 ps est généré entre les canaux de conduite. Dans notre deuxième contribution, nous présentons pour la première fois un nouveau fac-teur de mérite (FDM) pour les modulateurs SiP qui inclut non seulement la perte optique et l'efficacité (comme les FDMs précédents), mais aussi la bande passante électro-optique du modulateur SiP (BWEO). Ce nouveau FDM peut faire correspondre les paramètres de conception physique du modulateur SiP à ses critères de performance au niveau du système, facilitant à la fois la conception du dispositif optique et l'optimisation du système. Pour la première fois nous définissons et utilisons la pénalité de puissance du modulateur (MPP) induite par le modulateur SiP pour étudier la dégradation des performances au niveau du système induite par le modulateur SiP dans une communication à base de modulation d'amplitude d'impulsion optique. Nous avons développé l'équation pour MPP qui inclut les facteurs de limitation du modulateur (perte optique, taux d'extinction limité et limitation de la bande passante électro-optique). Enfin, dans notre troisième contribution, une nouvelle méthodologie de conception pour les modulateurs en SiP intégré à haute débit est présentée. La nouvelle approche est basée sur la minimisation de la MPP SiP en optimisant l'architecture du modulateur et le point de fonctionnement. Pour ce processus, une conception en longueur unitaire du modulateur Mach Zehnder (MZM) peut être optimisée en suivant les spécifications du procédé de fabrication et les règles de conception. Cependant, la longueur et la tension de biais du d'éphaseur doivent être optimisées ensemble (par exemple selon vitesse de transmission et format de modulation). Pour vérifier l'approche d'optimisation proposée expérimentale mont, a conçu un modulateur photonique sur silicium en phase / quadrature de phase (IQ) ciblant le format de modulation 16-QAM à 60 Gigabaud. Les résultats expérimentaux prouvent la fiabilité de la méthodologie proposée. D'ailleurs, nous avons augmenté la vitesse de transmission jusqu'à 70 Gigabaud pour tester la limite de débit au système. Une transmission de données dos à dos avec des débits binaires de plus de 233 Gigabit/s/channel est observée. Cette méthodologie de conception ouvre ainsi la voie à la conception de la prochaine génération d'émetteurs intégrés à double polarisation 400+ Gigabit/s/channel.Data-hungry applications (social media, video streaming, big data, etc.) are expanding at a fast pace, growing demand for ultra-fast optical links. This driving force reveals need for low-cost, integrated optical transmitters and pushes research in silicon photonics because of its advantages over other platforms (i.e. LiNbO3 and InP), such as compatibility with CMOS fabrication processes, the ability of on-chip polarization manipulation, and cost effciency. Electro-optic modulators are an essential component of optical communication links and immense research is dedicated to developing effcient high-bitrate devices. However, the design of high-capacity Silicon Photonics (SiP) transmitters is challenging, mainly due to lack of inherent electro-optic effect in silicon. New design methodologies and performance merits have to be developed in order to map the system-level criteria of an optical link to the design parameters in device-level. In addition, co-design of silicon photonics and CMOS integrated circuits is crucial to reveal the full potential of silicon photonics. This thesis addresses the aforementioned challenges. In our frst contribution, for the frst time we present a DAC-less PAM-4 silicon photonic transmitter that includes a SiP lumped-element segmented-electrode Mach Zehnder modula-tor (LES-MZM) implemented in a generic silicon photonic process with lateral p-n junction and its co-designed CMOS driver. Using post processing, bitrates up to 38 Gb/s/channel are achieved without using an external digital to analog converter. We also presents a novel delay generation procedure in the CMOS driver. A robust delay as small as 7 ps is generated between the driving channels. In our second contribution, for the frst time we present a new figure of merit (FOM) for SiP modulators that includes not only the optical loss and effciency (like the prior FOMs), but also the SiP modulator electro-optic bandwidth ( BWEO). This new FOM can map SiP modulator physical design parameters to its system-level performance criteria, facilitating both device design and system optimization. For the frst time we define and employ the modulator power penalty (MPP) induced by the SiP modulator to study the system level performance degradation induced by SiP modulator in an optical pulse amplitude modulation link. We develope a closed-form equation for MPP that includes the SiP modulator limiting factors (optical loss, limited extinction ratio and electro-optic bandwidth limitation). Finally in our third contribution, we present a novel design methodology for integrated high capacity SiP modulators. The new approach is based on minimizing the power penalty of a SiP modulator (MPP) by optimizing modulator design and bias point. For the given process, a unit-length design of Mach Zehnder modulator (MZM) can be optimized following the process specifications and design rules. However, the length and the bias voltage of the phase shifter must be optimized together in a system context (e.g., baud rate and modulation format). Moreover, to verify the proposed optimization approach in experiment, we design an in-phase/quadrature-phase (IQ) silicon photonic modulator targeting 16-QAM modulation format at 60 Gbaud. Experimental results proves the reliability of our proposed methodology. We further push the baud rate up to 70 Gbaud to examine the capacity boundary of the device. Back to back data transmission with bitrates more than 233 Gb/s/channel are captured. This design methodology paves the way for designing the next generation of integrated dual- polarization 400+ Gb/s/channel transmitters

Survey of Photonic and Plasmonic Interconnect Technologies for Intra-Datacenter and High-Performance Computing Communications

Large scale data centers (DC) and high performance computing (HPC) systems require more and more computing power at higher energy efficiency. They are already consuming megawatts of power, and a linear extrapolation of trends reveals that they may eventually lead to unrealistic power consumption scenarios in order to satisfy future requirements (e.g., Exascale computing). Conventional complementary metal oxide semiconductor (CMOS)-based electronic interconnects are not expected to keep up with the envisioned future board-to-board and chip-to-chip (within multi-chip-modules) interconnect requirements because of bandwidth-density and power-consumption limitations. However, low-power and high-speed optics-based interconnects are emerging as alternatives for DC and HPC communications; they offer unique opportunities for continued energy-efficiency and bandwidth-density improvements, although cost is a challenge at the shortest length scales. Plasmonics-based interconnects on the other hand, due to their extremely small size, offer another interesting solution for further scaling operational speed and energy efficiency. At the device-level, CMOS compatibility is also an important issue, since ultimately photonics or plasmonics will have to be co-integrated with electronics. In this paper, we survey the available literature and compare the aforementioned interconnect technologies, with respect to their suitability for high-speed and energy-efficient on-chip and offchip communications. This paper refers to relatively short links with potential applications in the following interconnect distance hierarchy: local group of racks, board to board, module to module, chip to chip, and on chip connections. We compare different interconnect device modules, including low-energy output devices (such as lasers, modulators, and LEDs), photodetectors, passive devices (i.e., waveguides and couplers) and electrical circuitry (such as laserdiode drivers, modulator drivers, transimpedance, and limiting amplifiers). We show that photonic technologies have the potential to meet the requirements for selected HPC and DC applications in a shorter term. We also present that plasmonic interconnect modules could offer ultra-compact active areas, leading to high integration bandwidth densities, and low device capacitances allowing for ultra-high bandwidth operation that would satisfy the application requirements further into the future

Energy Efficient and High Density Integrated Photonic Transceivers

Light, as a medium for communication, has the unique ability to transmit volumes of data with minimal energy loss. This capability not only sparked the revolution of internet-based communication over fiber optic networks, but also holds the potential to expand computing beyond our current capabilities. At present, data is stored densely in computer chips, but is sent out of the chip through centimeter-long electrical wires in a slow and energy-intensive process, before finally interfacing with optical transmitters. To bypass this bottleneck, electrical channels can be condensed and converted into light over a compact area using integrated photonic chips. In particular, the silicon photonics technology platform offers the potential for extremely dense data communications due to its high confinement waveguides and compact micro-resonators. However, three major obstacles stand in the way of realizing a low-energy and bandwidth-dense implementation of this technology: the integration of photonics with electronics, optical coupling from the photonic chip to fiber, and scaling up link architectures to multiplex data streams onto many wavelengths. The work in this thesis aims to confront these three challenges and advance integrated photonics technology to unprecedented bandwidth densities and energy efficiencies, with a focus on the first challenge of photonic-electronic integration. It begins with an overview of the escalating demand for inter-chip bandwidths and the potential solution offered by integrated photonics. Next, this thesis builds a theoretical framework for the performance parameters and sources of energy consumption that are addressed in the subsequent sections. After this introductory context, the thesis describes the achievement of the highest density and largest scale photonic-electronic integration to date, using a dense, 25 um pitch 3D bonding process. An 80-channel array fabricated in this integration records the lowest data link energies to date, at 120 fJ/bit, and transfers data at 10 Gbit/s/channel for a record 5.3 Tbit/s/mm2 bandwidth density. The discussion then shifts to the issue of chip-to-fiber coupling efficiency, traditionally the greatest source of loss in photonic links. A substrate-removed edge coupler design reduces this loss to a mere 1.1 dB, and an inverse-designed edge coupler taper shows a fourfold length reduction compared to linear tapers. Lastly, the thesis presents designs for wavelength scaling that increase the number of energy efficient channels on a single fiber. Specifically, it demonstrates a multi-channel, polarization diverse micro-comb receiver and a 3D-integrated transceiver with wavelength interleaving to waveguide buses of cascaded resonators. This thesis builds on photonic device developments to introduce photonic systems with the lowest energy and densest data communications to date. Together, these results unlock the tremendous potential of light as a fast and energy-efficient communication medium between chips, paving a sustainable path towards scaling artificial intelligence and disaggregating computation and memory resources

Design of clock and data recovery circuits for energy-efficient short-reach optical transceivers

Nowadays, the increasing demand for cloud based computing and social media services mandates higher throughput (at least 56 Gb/s per data lane with 400 Gb/s total capacity 1) for short reach optical links (with the reach typically less than 2 km) inside data centres. The immediate consequences are the huge and power hungry data centers. To address these issues the intra-data-center connectivity by means of optical links needs continuous upgrading. In recent years, the trend in the industry has shifted toward the use of more complex modulation formats like PAM4 due to its spectral efficiency over the traditional NRZ. Another advantage is the reduced number of channels count which is more cost-effective considering the required area and the I/O density. However employing PAM4 results in more complex transceivers circuitry due to the presence of multilevel transitions and reduced noise budget. In addition, providing higher speed while accommodating the stringent requirements of higher density and energy efficiency (< 5 pJ/bit), makes the design of the optical links more challenging and requires innovative design techniques both at the system and circuit level. This work presents the design of a Clock and Data Recovery Circuit (CDR) as one of the key building blocks for the transceiver modules used in such fibreoptic links. Capable of working with PAM4 signalling format, the new proposed CDR architecture targets data rates of 50−56 Gb/s while achieving the required energy efficiency (< 5 pJ/bit). At the system level, the design proposes a new PAM4 PD which provides a better trade-off in terms of bandwidth and systematic jitter generation in the CDR. By using a digital loop controller (DLC), the CDR gains considerable area reduction with flexibility to adjust the loop dynamics. At the circuit level it focuses on applying different circuit techniques to mitigate the circuit imperfections. It presents a wideband analog front end (AFE), suitable for a 56 Gb/s, 28-Gbaud PAM-4 signal, by using an 8x interleaved, master/ slave based sample and hold circuit. In addition, the AFE is equipped with a calibration scheme which corrects the errors associated with the sampling channels’ offset voltage and gain mismatches. The presented digital to phase converter (DPC) features a modified phase interpolator (PI), a new quadrature phase corrector (QPC) and multi-phase output with de-skewing capabilities.The DPC (as a standalone block) and the CDR (as the main focus of this work) were fabricated in 65-nm CMOS technology. Based on the measurements, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. Although the CDR was not fully operational with the PAM4 input, the results from 25-Gbaud PAM2 (NRZ) test setup were used to estimate the performance. Under this scenario, the 1-UI JTOL bandwidth was measured to be 2 MHz with BER threshold of 10−4. The chip consumes 236 mW of power while operating on 1 − 1.2 V supply range achieving an energyefficiency of 4.27 pJ/bit

Design of High-Speed CMOS Interface Circuits for Optical Communications

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 정덕균.The bandwidth requirement of wireline communications has increased ex-ponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effect, dielectric loss, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul net-works and metropolitan area networks, to the medium- and short-reach com-munication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challeng-es are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics that has long been investigated by a number of research groups. De-spite inherent incompatibility of silicon with the photonic world, silicon pho-tonics is promising and is the only solution that can leverage the mature CMOS technologies. In this thesis, we summarize the current status of silicon photonics and pro-vide the prospect of the optical interconnection. We also present key circuit techniques essential to the implementation of high-speed and low-power optical receivers. And then, we propose optical receiver architectures satisfying the aforementioned requirements with novel circuit techniques.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 6 CHAPTER 2 BACKGROUND OF OPTICAL COMMUNICATION 7 2.1 OVERVIEW OF OPTICAL LINK 7 2.2 SILICON PHOTONICS 11 2.3 HYBRID INTEGRATION 22 2.4 SILICON-BASED PHOTODIODES 28 2.4.1 BASIC TERMINOLOGY 28 2.4.2 SILICON PD 29 2.4.3 GERMANIUM PD 32 2.4.4 INTEGRATION WITH WAVEGUIDE 33 CHAPTER 3 CIRCUIT TECHNIQUES FOR OPTICAL RECEIVER 35 3.1 BASIS OF TRANSIMPEDANCE AMPLIFIER 35 3.2 TOPOLOGY OF TIA 39 3.2.1 RESISTOR-BASED TIA 39 3.2.2 COMMON-GATE-BASED TIA 41 3.2.3 FEEDBACK-BASED TIA 44 3.2.4 INVERTER-BASED TIA 47 3.2.5 INTEGRATING RECEIVER 48 3.3 BANDWIDTH EXTENSION TECHNIQUES 49 3.3.1 INDUCTOR-BASED TECHNIQUE 49 3.3.2 EQUALIZATION 61 3.4 CLOCK AND DATA RECOVERY CIRCUITS 66 3.4.1 CDR BASIC 66 3.4.2 CDR EXAMPLES 68 CHAPTER 4 LOW-POWER OPTICAL RECEIVER FRONT-END 73 4.1 OVERVIEW 73 4.2 INVERTER-BASED TIA WITH RESISTIVE FEEDBACK 74 4.3 INVERTER-BASED TIA WITH RESISTIVE AND INDUCTIVE FEEDBACK 81 4.4 CIRCUIT IMPLEMENTATION 89 4.5 MEASUREMENT RESULTS 93 CHAPTER 5 BANDWIDTH- AND POWER-SCALABLE OPTICAL RECEIVER FRONT-END 96 5.1 OVERVIEW 96 5.2 BANDWIDTH AND POWER SCALABILITY 97 5.3 GM STABILIZATION 98 5.4 OVERALL BLOCK DIAGRAM OF RECEIVER 104 5.5 MEASUREMENT RESULTS 111 CHAPTER 6 CONCLUSION 118 BIBLIOGRAPHY 120 초 록 131Docto