On-chip wires will present increasing latency and energy problems as VLSI technologies continue to scale. Interconnects have an RC-limited bandwidth approximately proportional to the area of the metal cross section and inversely proportional to the squared length. To overcome RC-limited channels, an energy-efficient on-chip transceiver is presented that contains a hybrid transmitter, a current-sense receiver, and self-testing blocks. The main goal of this research is having a relatively low-power transceiver, which can be used as an on-chip communication system.
By adding a pre-emphasis circuit in the transmitter, pre-cursor inter-symbol interference can be canceled. A hybrid transmitter which combines voltage-mode pre-emphasis with a current-mode main driver is used. This structure can save pre-emphasis current, and leads to reduced power dissipation especially in the static situation. A current-sense amplifier is implemented with a cross-coupled stage and an active inductor equalizer at the receiver, in order to boost the data rate while maintaining good energy efficiency. An offset cancelation circuit is incorporated to make a robust comparator for the receiver. According to simulation results, the transceiver has low power consumption with 1.2 V, 130 nm CMOS technology. The performance shows that it operates at 8 Gb/s over a 5 mm and 19 dB loss differential channel. The overall dynamic power consumption is 2.05 mW, without the PRBS generator/checker. Therefore, this transceiver has high data rate and low power consumption
