Impact of gate-level clustering on automated system partitioning of 3D-ICs

When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. Gate clustering is even more important for netlist partitioning targeting 3D system integration. In this paper, we make the argument that the choice of clustering method for 3D-ICs partitioning is not trivial and deserves careful consideration. To support our claim, we implemented three clustering methods that were used prior to partitioning two synthetic designs representing two extremes of the circuits medium/long interconnect diversity spectrum. Automatically partitioned netlists are then placed and routed in 3D to compare the impact of clustering methods on several metrics. From our experiments, we see that the clustering method indeed has a different impact depending on the design considered and that a circuit-blind, universal partitioning method is not the way to go, with wire-length savings of up to 31%, total power of up to 22%, and effective frequency of up to 15% compared to other methods. Furthermore, we highlight that 3D-ICs open new opportunities to design systems with a denser interconnect, drastically reducing the design utilization of circuits that would not be considered viable in 2D.Comment: 8 pages, 6 figure

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap

The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies

Optimal Power Delivery Strategy in Modern VLSI Design

Department of Electrical EngineeringIn a modern very-large-scale integration (VLSI) designs, heterogeneous architectural structures and various three-dimensional (3D) integration methods have been used in a hybrid manner. Recently, the industry has combined 3D VLSI technology with the heterogeneous technology of modern VLSI called chiplet. The 3D heterogeneous architectural structure is growing attention because it reduces costs and time-to-market by increasing manufacturing yield with high integration rate and modularization. However, a main design concern of heterogeneous 3D architectural structure is power management for lowering power consumption with maintaining the required power integrity from IR drop. Although the low-power design can be realized in front-end-of-line level by reduced power supply complementary metal???oxide???semiconductor technologies, the overall low-power system performance is available with a proper design of power delivery network (PDN) for chip-level modules and system-level architectural structure. Thus, there is a demand for both the coanalysis and optimization for both chip-level and system-level. We analyzed and optimized power delivery on-chip in various 3D integration environments, and we also have proposed a chip-package-PCB coanalysis methodology at the system level. For through-silicon-via (TSV)-based 3D integration circuit (IC), We have investigated and analyzed the voltage noise in a multi-layer 3D stacking with partial element equivalent circuit (PEEC)-based on-chip PDN and frequency-dependent TSV models. We also have proposed a wire-added multi-paired on-chip PDN structure to reduce voltage noise to reduce IR drop. The performance of TSV-based 3D ICs has also been improved by reducing wake-up time through our proposed adaptive power gating strategy with tapered TSVs. For die-to-wafer 3D IC, we have proposed a power delivery pathfinding methodology, which seeks to identify a nearly optimal PDN for a given design and PDN specification. Our pathfinding methodology exploits models for routability and worst IR drop, which helps reducing iterations between PDN design and circuit design in 3D IC implementation. We also have extended the observation to system-level, we have proposed a power integrity coanalysis methodology for multiple power domains in high-frequency memory systems. Our coanalysis methodology can analyze the tendencies in power integrity by using parametric methods with consideration of package-on-package integration. We have proved that our methodology can predict similar peak-to-peak ripple voltages that are comparable with the realistic simulations of high-speed low-power memory interfaces. Finally, we have proposed analysis and optimization methodologies that are generally applicable to various integration methods used in modern VLSI designs as computer-aided-design-based solutions.clos

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Improved Physical Design for Manufacturing Awareness and Advanced VLSI

Increasing challenges arise with each new semiconductor technology node, especially in advanced nodes, where the industry tries to extract every ounce of benefit as it approaches the limits of physics, through manufacturing-aware design technology co-optimization and design-based equivalent scaling. The increasing complexity of design and process technologies, and ever-more complex design rules, also become hurdles for academic researchers, separating academic researchers from the most up-to-date technical issues.This thesis presents innovative methodologies and optimizations to address the above challenges. There are three directions in this thesis: (i) manufacturing-aware design technology co-optimization; (ii) advanced node design-based equivalent scaling; and (iii) an open source academic detailed routing flow.To realize manufacturing-aware design technology co-optimization, this thesis presents two works: (i) a multi-row detailed placement optimization for neighbor diffusion effect mitigation between neighboring standard cells; and (ii) a post-routing optimization to generate 2D block mask layout for dummy segment removal in self-aligned multiple patterning.To achieve advanced node design-based equivalent scaling, this thesis presents two improved physical design methodologies: (i) a post-placement flop tray generation approach for clock power reduction; and (ii) a detailed placement approach to exploit inter-row M1 routing for congestion and wirelength reduction.To address the increasing gap between academia and industry, this thesis presents two works toward an open source academic detailed routing flow: (i) a complete, robust, scalable and design ruleaware dynamic programming-based pin access analysis framework; and (ii) TritonRoute – the open source detailed router that is capable of delivering DRC-clean detailed routing solutions in advanced nodes.This thesis concludes with a summary of its contributions and open directions for future research

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects

리소그래피 패턴 정렬용 생성적 적대 신경망의 강건한 훈련을 위한 효과적인 데이터 선택

학위논문(석사) -- 서울대학교대학원 : 공과대학 기계공학부, 2023. 2. 김도년.Critical Dimension SEM (CD-SEM) is a dedicated system for measuring the shape, size and roughness of patterns formed on semiconductor wafers. As designs shrink and product development challenges increase, the ability to quickly measure large amounts of samples for accurate Optical Proximity Correction (OPC) is required. Design Based Metrology (DBM) technology allowed the rapid creation of large volumes of recipes using design images and reduced measurement time. However, there were still many problems in the alignment between the design image and the SEM image, and to solve this problem, a new pattern alignment method using Generative Adversarial Network (GAN) technology was developed. In this paper, training patterns are classified according to polygon types of design patterns and the alignment effect according to each type is confirmed. We also studied how to effectively select a training set for model training through the relationship between training set and alignment accuracy.Critical Dimension SEM(CD-SEM)은 반도체 웨이퍼에 형성된 패턴의 모양, 크기 및 거칠기를 측정하는 전용 시스템이다. 설계가 축소되고 제품 개발 과제가 증가함에 따라 정확한 Optical Proximity Correction (OPC)를 위해 대량의 샘플을 신속하게 측정할 수 있는 기능이 필요하다. Design Based Metrology (DBM) 기술을 통해 설계 이미지를 사용하여 대량의 레시피를 빠르게 생성하고 측정 시간을 단축할 수 있었다. 그러나 디자인 이미지와 SEM 이미지 간의 정렬에는 여전히 많은 문제가 있었고, 이를 해결하기 위해 Generative Adversarial Network (GAN) 기술을 사용한 새로운 패턴 정렬 방법이 개발되었다. 본 논문에서는 디자인 패턴의 폴리곤 유형에 따라 학습 패턴을 분류하고 각 유형에 따른 정렬 효과를 확인하였다. 또한 훈련 세트와 정렬 정확도의 관계를 통해 모델 훈련을 위한 훈련 세트를 효과적으로 선택하는 방법을 연구하였다.Chapter 1. Introduction 1 1-1. Semiconductor design and optical proximity correction 2 1-2. SEM inspection and design-based metrology 5 1-3. A new method of lithography pattern alignment 9 Chapter 2. Motivation 16 2-1. Relationship between accuracy and sample set 17 Chapter 3. Experiments 24 3-1. Relationship between train pattern size and alignment result 26 3-1-1. The result of inferring an image twice the size of the pattern learned by the model 28 3-1-2. The result of inferring an image three times the size of the pattern learned by the model 29 3-1-3. The result of inferring an image four times the size of the pattern learned by the model 30 3-2. Dense-to-iso or iso-to-dense pattern relationship 32 3-2-1. Dense to iso pattern relationship 33 3-2-2. Iso to dense pattern relationship 34 3-3. The Pattern shifted and direction 35 Chapter 4. Methodology and Result 39 4-1. How to select the minimum sample that can cover the entire pattern 42 4-2. Proposed method and improvement 45 4-2-1. Proposed method 46 4-2-2. Improvement using effective distance based pattern extraction 49 Chapter 5. Conclusion 56 Bibliography 59 Abstract in Korean 66석

Développement d’un procédé d’électrodéposition séquentielle pour fabrication des microbilles à haute densité

Aujourd’hui l’industrie des semiconducteurs aborde une époque requérant le couplage de l’innovation au niveau de l'assemblage avec la mise à l’échelle des dispositifs. Cette dernière n’est plus l’élément clé qui propulse l’évolution technologique à cause de l’énorme investissement requis vis-à-vis sa rentabilité qui devient de plus en plus limitée. Avec la réorientation de l’intérêt de la majorité des acteurs vers l’innovation au niveau des assemblages, cette thèse s’inscrit dans un contexte d’amélioration de la fiabilité des assemblages de larges puces renversées pour le calul haute performance à travers le développement des microbilles de brasures à faible coût et de métallurgie optimisée. Des microbilles de brasure à faible coût et hétérogènes sont proposées comme une approche simple qui présente des bénéfices métallurgiques et économiques. D’une part, l’électrodéposition séquentielle des couches de Sn et Ag pures au lieu d’alliage est réalisée à un faible coût d’acquisition et avec une simplicité de maintenance. D’une autre part, la même installation d’électrodéposition de Sn et Ag purs peut servir à la fabrication d’une multitude de brasures avec différentes teneurs en Ag. Malgré le besoin d’une standardisation des procédés de fabrication des microbilles, les motivations citées précédemment peuvent constituer un facteur d’attraction pour l’industrie afin de l’adopter comme alternative à l’électrodéposition conventionnelle des alliages. En plus de son faible coût, l’approche de fabrication des microbilles par électrodéposition séquentielle amène une flexibilité métallurgique avec l’utilisation d’une barrière qui limite la diffusion d’Ag. Cette dernière résulte en une microbille de brasure unique, qui peut à la fois i) avoir une structure hétérogène avec une faible teneur en Ag dont la ductilité élevée est maintenue à proximité des couches fragiles de la métallisation de la puce lors des étapes de l’assemblage; ii) avoir une forme en pilier dont des bénéfices sont similaires à ceux du pilier en Cu en évitant les effets néfastes de sa rigidité sur les couches du BEOL. Les différentes étapes de fabrication des microbilles de brasure ont été développées en se limitant à des procédés qui peuvent être intégrés facilement dans un environnement de production industrielle. La manipulation de la métallurgie des joints de brasure a été réalisée avec succès en démontrant une structure hétérogène unique de brasure dans un assemblage de puces renversées