System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude

Intellectual property related development aid: is supply aligned with demand?

We assessed to what extent developed country development aid programmes are likely to have interacted with, and potentially contributed to the promotion of country-appropriate sustainable changes in IP strategies and technological capacities over the period 2005-10. This was done primarily on the basis of an imputed impact assessments of four emerging and transition economies; namely Brazil, India, Poland and Thailand. Through an analysis of various measures of the domestic economic, technological and Intellectual Property context, we studied to what extent the supply of IP-related development aid provided between 2005 and 2010 responded to the likely needs of recipient countries. While the data shows that technical and financial assistance in this area could be of great use, and there is clearly a need for well-targeted IP TA and much scope for useful IP TA interventions, there seemed to only be a partial alignment between country needs and the direction of IP TA. On the whole, most IP-related development aid and technical assistance ended to focus on similar areas in each country, regardless of the development context. In Brazil and India’s case, training on IP administration may have influenced increased efficiency (from a low base) at the INPI and IP India, while the substantial EU support to raise SME IP awareness in Poland is likely to have had some significant impacts. In India, sustained development aid in this area likely influenced legislation on plant variety protection, as did WIPO TA on legislative reforms in Thailand. In all cases, the substantial US (and to a more limited extent EC) focus on development aid directed towards enforcement coincided with improvements in this area, though the political and economic pressures by both providers, and especially the US Section 301 System probably dwarfed the impact of this type of aid. Further, the typology and direction of IP related development aid reflects the comparative advantage of IP TA providers, as well as political and diplomatic interests, trade priorities and colonial ties, among many other things. As such, it is important to understand that IP TA is also highly political – a fact often concealed in the emphasis on its “technical” nature.Intellectual Property and development, aid and technical assistance technological capacities in Brazil, India, Poland, Thailand, taxonomy of development, funding flows Intellectual Property and development, aid and technical assistance technological capacities in Brazil, India, Poland, Thailand, taxonomy of development, funding flows Intellectual Property and development, aid and technical assistance, technological capacities in Brazil, India, Poland, Thailand, taxonomy of development, funding flows Intellectual Property and development, aid and technical assistance technological capacities in Brazil, India, Poland, Thailand, taxonomy of development, funding flows

Model-Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification

Spectre and Meltdown attacks in modern microprocessors represent a new class of attacks that have been difficult to deal with. They underline vulnerabilities in hardware design that have been going unnoticed for years. This shows the weakness of the state-of-the-art verification process and design practices. These attacks are OS-independent, and they do not exploit any software vulnerabilities. Moreover, they violate all security assumptions ensured by standard security procedures, (e.g., address space isolation), and, as a result, every security mechanism built upon these guarantees. These vulnerabilities allow the attacker to retrieve leaked data without accessing the secret directly. Indeed, they make use of covert channels, which are mechanisms of hidden communication that convey sensitive information without any visible information flow between the malicious party and the victim. The root cause of this type of side-channel attacks lies within the speculative and out-of-order execution of modern high-performance microarchitectures. Since modern processors are hard to verify with standard formal verification techniques, we present a methodology that shows how to transform a realistic model of a speculative and out-of-order processor into an abstract one. Following related formal verification approaches, we simplify the model under consideration by abstraction and refinement steps. We also present an approach to formally verify the abstract model using a standard model checker. The theoretical flow, reliant on established formal verification results, is introduced and a sketch of proof is provided for soundness and correctness. Finally, we demonstrate the feasibility of our approach, by applying it on a pipelined DLX RISC-inspired processor architecture. We show preliminary experimental results to support our claim, performing Bounded Model-Checking with a state-of-the-art model checker

Evolutionary Synthesis of Cube Root Computational Circuit Using Graph Hybrid Estimation of Distribution Algorithm

The paper is focused on evolutionary synthesis of analog circuit realization of cube root function using proposed Graph Hybrid Estimation of Distribution Algorithm. The problem of cube root function circuit realization was adopted to demonstrate synthesis capability of the proposed method. Individuals of the population of the proposed method which represent promising topologies are encoded using graphs and hypergraphs. Hybridization with local search algorithm was used. The proposed method employs univariate probabilistic model

Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors

Specific features of Wireless Sensor Networks (WSNs) like the open accessibility to nodes, or the easy observability of radio communications, lead to severe security challenges. The application of traditional security schemes on sensor nodes is limited due to the restricted computation capability, low-power availability, and the inherent low data rate. In order to avoid dependencies on a compromised level of security, a WSN node with a microcontroller and a Field Programmable Gate Array (FPGA) is used along this work to implement a state-of-the art solution based on ECC (Elliptic Curve Cryptography). In this paper it is described how the reconfiguration possibilities of the system can be used to adapt ECC parameters in order to increase or reduce the security level depending on the application scenario or the energy budget. Two setups have been created to compare the software- and hardware-supported approaches. According to the results, the FPGA-based ECC implementation requires three orders of magnitude less energy, compared with a low power microcontroller implementation, even considering the power consumption overhead introduced by the hardware reconfiguratio

A review of architectures and concepts for intelligence in future electric energy system

Renewable energy sources are one key enabler to decrease greenhouse gas emissions and to cope with the anthropogenic climate change. Their intermittent behavior and limited storage capabilities present a new challenge to power system operators to maintain power quality and reliability. Additional technical complexity arises from the large number of small distributed generation units and their allocation within the power system. Market liberalization and changing regulatory framework lead to additional organizational complexity. As a result, the design and operation of the future electric energy system have to be redefined. Sophisticated information and communication architectures, automation concepts, and control approaches are necessary in order to manage the higher complexity of so-called smart grids. This paper provides an overview of the state of the art and recent developments enabling higher intelligence in future smart grids. The integration of renewable sources and storage systems into the power grids is analyzed. Energy management and demand response methods and important automation paradigms and domain standards are also reviewed.info:eu-repo/semantics/publishedVersio

Strategic Alliances in the European Industries of the Third Industrial Revolution

The dimension of the alliances has compelled experts to revise their preconceptions about the internationalization of companies and to include this strategy in their models as Uppsala model was forced to acknowledge. This article focuses on one of the alliances forged in Europe, very deviated from the practices of the majority because it was a company with exclusively European partners. It adopts the perspective of a peripheral country (Spain) in the global economy and from the special status of at least one of the partners in a monopoly. Finally, the article follows case study methodology, which aims to delve into the complexity of the processes and the phenomena at hand. The article responds to the need for an alternative approach to industry analysis that is particularly important for technology-based industries and the most turbulent high-tech industries.  The first section examines the creation of European Silicon Structures as a strategic alliance in the European semiconductor industry. Parts two and three look at the case of Spain and the role of demand using the example of Telefonica. Conclusions are presented in the final section