Current error compensation for current-sensorless power factor corrector stage in continuous conduction mode

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. V. M. Lopez-Martin, F. J. Azcondo, and A. de Castro, "Current error compensation for current-sensorless power factor corrector stage in continuous conduction mode", 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics (COMPEL), Kyoto (Japan), 2012, pp. 1-8A universal digital PFC current-sensorless controller based on control of estimated current is presented. Parasitic elements cause a small difference between the measured input voltage and the voltage across the inductance in a boost converter, which must be taken into account to estimate the input current in a sensorless PFC digital controller. To compensate for the deviation caused by the parasitic elements, and so minimize the current estimation error, the article proposes a digital feedback control technique that cancels the time difference between DCM operation time of the real input current (TinDCM) and the estimated current (TrebDCM). Experimental results, obtained using a boost PFC converter under different conditions, are shown for verification purposes.This work was supported by the Spanish Ministry of Science TEC FEDER 2011-2361

Universal Digital Controller for Boost CCM Power Factor Correction Stages Based on Current Rebuilding Concept

Continuous conduction mode power factor correction (PFC) without input current measurement is a step forward with respect to previously proposed PFC digital controllers. Inductor volt-second (vsL) measurement in each switching period enables digital estimation of the input current; however, an accurate compensation of the small errors in the measured vsL is required for the estimation to match the actual current. Otherwise, they are accumulated every switching period over the half-line cycle, leading to an appreciable current distortion. A vsL estimation method is proposed, measuring the input (vg) and output voltage (vo). Discontinuous conduction mode (DCM) occurs near input line zero crossings and is detected by measuring the drain-to-source MOSFET voltage vds. Parasitic elements cause a small difference between the estimated voltage across the inductor based on input and output voltage measurements and the actual one, which must be taken into account to estimate the input current in the proposed sensorless PFC digital controller. This paper analyzes the current estimation error caused by errors in the ON-time estimation, voltage measurements, and the parasitic elements. A new digital feedback control with high resolution is also proposed. It cancels the difference between DCM operation time of the real input current, (TDCMg) and the estimated DCM time (TDCMreb). Therefore, the current estimation is calibrated using digital signals during operation in DCM. A fast feedforward coarse time error compensation is carried out with the measured delay of the drive signal, and a fine compensation is achieved with a feedback loop that matches the estimated and real DCM time. The digital controller can be used in universal applications due to the ability of the DCM time feedback loop to autotune based on the operation conditions (power level, input voltage, output v- ltage...), which improves the operation range in comparison with previous solutions. Experimental results are shown for a 1-kW boost PFC converter over a wide power and voltage range

High-resolution error compensation in continuous conduction mode power factor correction stage without current sensor

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. V. M. López-Martín, F. J. Azcondo, and Á. de Castro, "High-resolution error compensation in continuous conduction mode power factor correction stage without current sensor", in 2012 15th International Power Electronics and Motion Control Conference (EPE/PEMC), Novi Sad (Serbia), 2012.Continuous conduction mode power factor correction (PFC) without input current measurement is a step forward with respect to previously proposed PFC digital controllers. Inductance volt-second (vsL) measurement in each switching period enables the estimation of input current, but an accurate compensation of the small errors in the measured vsL is required. Otherwise, they are accumulated over a half-cycle line, leading to an appreciable current distortion. A vsL estimation is proposed, measuring the input (vin) and the the output voltage (vo). Discontinuous conduction mode (DCM) occurs near input line zero crossings, and is also detected by measuring MOSFET vds. This article analyzes the current estimation error caused by errors in the on-time estimation and voltage measurements, and proposes the minimization of vsL errors by cancelling the difference between estimated DCM (TDCMinereb) and real DCM (TDCMin) times with a signal (vdig), generated in the digital device. Therefore, the current estimation is calibrated using digital signals during the operation in DCM. Feedfoward coarse time error compensation is carried out with the measured delay of the drive signal, and then a fine compensation is achieved with a feedback loop that adjusts vdig. Experimental results are shown for a 1 kW boost PFC converter.This work was supported in part by the Spanish Ministry of Science TEC - FEDER 2011-2361

Adaptive Boundary Control Using the Natural Switching Surfaces for Flyback Converters

The derivation and implementation of the natural switching surfaces (NSS) considering certain parametric uncertainties for a flyback converter operating in the boundary conduction mode (BCM) is the main focus of this paper. The NSS with nominal parameters presents many benefits for the control of nonlinear systems; for example, fast transient response under load-changing conditions. However, the performance worsens considerably when the converter actual parameters are different from the ones used in the design process. Therefore, a novel control strategy for NSS considering the effects of parameter uncertainties is proposed. This control law can estimate and adapt the control trajectories in a minimum number of switching cycles to obtain excellent performances even under extreme parameter uncertainties. The analytical derivation of the proposed adaptive switching surfaces is presented together with simulations and experimental results showing adequate performance under different tests, including comparisons with a standard PI controller

Power quality enhancement in residential smart grids through power factor correction stages

The proliferation of non-linear loads and the increasing penetration of Distributed Energy Resources (DER) in Medium-Voltage (MV) and Low-Voltage (LV) distribution grids, make it more difficult to maintain the power quality levels in residential electrical grids, especially in the case of weak grids. Most household appliances contain a conventional Power Factor Corrector (PFC) rectifier, which maximizes the load Power Factor (PF) but does not contribute to the regulation of the voltage Total Harmonic Distortion (THDV) in residential electrical grids. This manuscript proposes a modification for PFC controllers by adapting the operation mode depending on the measured THDV. As a result, the PFCs operate either in a low current Total Harmonic Distortion (THDI) mode or in the conventional resistor emulator mode and contribute to the regulation of the THDV and the P F at the distribution feeders. To prove the concept, the modification is applied to a current sensorless Non-Linear Controller (NLC) applied to a single-phase Boost rectifier. Experimental results show its performance in a PFC front-end stage operating in Continuous Conduction Mode (CCM) connected to the grid with different THDV.This work is funded by the Spanish Ministry of Science and Innovation through the project TEC2014-52316-R ECOTREND Estimation and Optimal Control for Energy Conversion with Digital Devices

AC mains synchronization loop for precalculated-based PFC converters using the output voltage measure

Common implementations of power factor correction include sensors for the input and output voltages and the input current. Many alternatives have been considered to reduce the number of sensors, especially the current sensor. One strategy is to precalculate the duty cycles that must be applied to every ac main, so the system only needs to synchronize them with the input voltage, and include a simple output voltage loop. The main problem with this approach is the sensibility to any synchronization error, because the input current is not measured, so its evolution is not continuously corrected. This paper shows how the synchronization error alters the current and the power factor, and it proposes several methods to detect and correct this error. All methods use the output voltage ADC, which is already used to control the output voltage, so the cost of the system is not increased. This technique can also be applied to any current sensorless PFC converter, because they are usually affected by leading or lagging currents, so the synchronization can be modified to reduce these effects. Results show that the implementation of this synchronization loop keeps a high-power factor under a wide synchronization error range, while the added logic is not significant.This research was funded by Spanish Ministerio de Economía y Competitividad grant number TEC2013-43017-R

Single ADC Digital PFC Controller Using Precalculated Duty Cycles

Traditional digital power factor correction (PFC) uses three sensors to measure the input and output voltages and the input current. Each sensor, especially the input current one, increases the cost of the system and generates power losses in case of resistive sensors. This paper presents a controller for boost PFC converters. It uses precalculated duty cycles generated offline, and applies them to the switch. In order to control the converter with nonnominal conditions, just one analog-to-digital converter (ADC) is used, whichmeasures the output voltage.Measuring the average and the ripple of the output voltage with this ADC, the controller takes compensation action for changes in the input voltage but also in the load of the converter. The average value is used to control the input voltage changes, while the ripple value is used to control load changes. These two loops present low frequency bandwidth, so the ADC and the whole system can be low cost. Finally, a comparator is used to detect the zero-crossing of the input voltage, so the precalculated values are synchronized with the ac mains. In this way, the converter only uses one ADC and one comparator, both with lowbandwidth. Results showthat high power factor and normative compliance are reached, even under nonnominal conditions

Digital Control Techniques for Efficiency Improvements in Single-Phase Boost Power Factor Correction Rectifiers

Input current shaping has been required in AC-DC rectifiers in order to comply with regulations that specify limits on input current harmonics. Boost power factor correction (PFC) rectifiers are widely used to achieve near-unity input power factor and low current harmonic distortion. This thesis addresses digital control techniques aimed at improving efficiency and reducing harmonic distortion in digitally controlled single-phase boost PFC rectifiers operating over wide range of loads. By taking advantage of the flexibility of digital controllers and using a discontinuous conduction mode (DCM) detection circuit, several proposed control techniques achieve low current harmonic distortion and improve system efficiency over wide load range in DCM and in continuous conduction mode (CCM). In heavy load operation, a simple passive power sharing technique is introduced for interleaved boost PFC rectifiers to increase system power modularity; in medium to light load operation, proposed adaptive approaches improve light load efficiency by extending switching period to achieve low voltage switching and by adjusting switching frequency to scale with processed power. Furthermore, a new current error estimation approach is applied to relieve current sensing limitations and to reduce current controller design effort. Digital control techniques are implemented and verified using field programmable gate array (FPGA) in several boost PFC rectifier prototypes

Input and output total currents characterization in BCM and CCM Interleaved Power Converters Under Inductance Mismatch

This paper presents a complete characterization of input and output currents in interleaved power converters with inductance mismatch, operating in Boundary Conduction Mode (BCM) and Continuous Conduction Mode (CCM). The proposal allows to compute these currents in several interleaved converter topologies for the entire range of operating points, considering any number of phases and any inductance ratio. Input and output currents are recovered from the values obtained when adding the phase currents in the instants where the slopes change; values that are thus defined as key points. This methodology is based on the coincidences that exist between the instants of the phase current key points and those of total currents. By using the computed key points, ripple amplitude, rms value and harmonic content of input and output total currents for the entire range of operating points can be easily obtained. Simulations are conducted on a 5-phase boost converter and a 5-phase buck converter under different conditions in order to validate the proposal expressions. Experimental tests on a 5- phase buck converter are presented under different operation conditions to verify that the proposed method can be applied in real situation.Fil: Cervellini, María Paula. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; ArgentinaFil: Carnaghi, Marco. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; ArgentinaFil: Antoszczuk, Pablo Daniel. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; ArgentinaFil: Garcia Retegui, Rogelio Adrian. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; ArgentinaFil: Funes, Marcos Alan. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; Argentin

Hardware-in-the-loop and digital control techniques applied to single-phase PFC converters

Power electronic converters for power factor correction (PFC) play a key role in single-phase electrical power systems, ensuring that the line current waveform complies with the applicable standards and grid codes while regulating the DC voltage. Its verification implies significant complexity and cost, since it requires long simulations to verify its behavior, for around hundreds of milliseconds. The development and test of the controller include nominal, abnormal and fault conditions in which the equipment could be damaged. Hardware-in-the-loop (HIL) is a cost-effective technique that allows the power converter to be replaced by a real-time simulation model, avoiding building prototypes in the early stages for the development and validation of the controller. However, the performance-vs-cost trade-off associated with HIL techniques depends on the mathematical models used for replicating the power converter, the load and the electrical grid, as well as the hardware platform chosen to build it, e.g., microprocessor or FPGA, and the required number of channels and I/O types to test the system. This work reviews state-of-the-art HIL techniques and digital control techniques for single-phase PFC converters.This research was funded by the Spanish Ministry of Science and Innovation under Project RTI2018-095138-B-C31 PEGIA—Power Electronics for the Grid and Industry Applications