Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics

Photodiodes and Image Sensors on Mechanically Flexible Ultra-Thin Silicon Chips-in-Foil

CMOS-Bildsensoren haben in den letzten zwei Jahrzehnten enorme technologische Fortschritte erfahren und sich als eine wettbewerbsfähige Alternative gegenüber CCDBildsensoren auf dem Markt etabliert. Reduziert man die Chipdicke von CMOSBildsensoren von normal 725 μm auf ≤ 30 μm, erhält man mechanisch flexible Bildaufnehmer. Gewölbte CMOS-Bildsensoren würden für die optische Wahrnehmung völlig neue Möglichkeiten eröffnen (wie z. B. bei Insektenaugen). Betrachtet man die auf dem Chip integrierten Bauelemente und Schaltungen unter mechanischen Spannungen, stellt man fest, dass ihre elektrischen und optoelektronischen Eigenschaften von der ausgeübten mechanischen Spannung beeinflusst werden. Für den technischen Einsatz ist eine vom mechanischen Zustand des Bildsensors unbeinflusste Funktion erforderlich. Der Einfluss von mechanischer Spannung auf die Bauelemente- und Schaltungs-Charakteristiken und seine Minimierung bzw. Kompensation sind daher von besonderem Interesse. In dieser Arbeit wurden die optischen und elektrischen Eigenschaften von passiven und aktiven Bauelementen, sowie integrierten Schaltungen auf monokristallinen gedünnten flexiblen Siliziumchips unter mechanischen Spannungen untersucht. Der Einfluss von mechanischen Spannungen auf optische Eigenschaften (spektrale Lichtempfindlichkeit, Dunkelstrom und elektronisches Rauschen) einzelner p-n-Übergang basierter Photodioden und Bildsensorarrays auf (100)-Siliziumwafern wurde theoretisch modelliert und experimentell charakterisiert. Weiterhin wurden die elektrischen Eigenschaften (Ladungsträgerbeweglichkeit, Schwellenspannung, 1/f Rauschen) von MOSFeldeffekttransistoren in Bezug auf mechanischen Spannungen charakterisiert und ihre Abhängigkeit von der Orientierung zur Kristallorientierung des Substrats untersucht. Integrierte Schaltungen, wie Bandgap-Referenzspannungsquellen, Operationsverstärker und SC-basierte Schaltungen wurden unter mechanischen Spannungen theoretisch betrachtet, entworfen, gefertigt und experimentell charakterisiert. Mit Hilfe des in dieser Arbeit vorgeschlagenen und eingesetzten Simulationskonzeptes, ist die Schaltungssimulation der obengenannten Abhängigkeiten möglich. Dadurch hat der Schaltungsentwickler die Möglichkeit Schaltungskonzepte zur Kompensation oder Minimierung der von der mechanischen Spannung hervorgerufenen Einflüsse zu simulieren. In dieser Hinsicht werden Schaltungskonzepte und Design-Regeln präsentiert, die den Einfluss von mechanischen Spannungen auf Bildsensorchips berücksichtigen und minimieren. Im Rahmen dieser Arbeit wurde darüber hinaus ein mechanisch flexibler Bildsensorchip entworfen, simuliert und gefertigt, dessen Betrieb unabhängig von der ausgeübten mechanischen Spannung ist. Der ultra-dünne 20 μm Bildsensorchip ist geeignet auf zylindrisch gewölbte Oberflächen aufgebracht zu werden und erlaubt die Aufnahme raumrichtungsselektiver optischer Informationen im Sinne eines Panoramablicks.CMOS image sensors (CIS) have experienced the last two decades tremendous technological advances rendering them a viable alternative to charged couple devices (CCDs) not only in high volume applications but also in applications which require high spatial and temporal resolution, high dynamic range, low noise or high sensitivity levels. CISs are employed due to their increased chip thickness (ca. 750 μm) solely in the traditional planar image acquisition. If the chip thickness could be reduced down to or less than 30 μm, the silicon chips would become mechanically flexible. Such flexible CISs could substantially extend the application spectrum of image sensors in non-conventional imaging systems (e.g. imitating insect vision). However, the on-chip integrated devices and circuits exhibit stress-induced changes on their electrical and optoelectronic characteristics. Since a stress independent operation is striven, the minimization or compensation of the influence of mechanical stress on the characteristics of devices and circuits is of great interest. In this work optical and electrical properties of passive and active devices as well as integrated circuits on ultra-thin monolithic flexible silicon chips have been investigated under the application of mechanical stress. The influence of mechanical stress on the optical characteristics (spectral sensitivity, dark current and electronic noise) of p-n junction based photodiodes and image sensor chips on (100)-silicon wafers have been theoretically modeled and experimentally characterized. Moreover, the electrical characteristics (carrier mobility, threshold voltage and 1/f noise) of mechanically strained MOS field-effect transistors and their dependence on the channel orientation on the substrate have been investigated. Integrated circuits such as bandgap reference voltage sources, operational amplifiers and switched capacitor (SC) based circuits have been theoretically treated, designed, fabricated and experimentally characterized. Within this framework a simulation technique has been proposed and deployed, which allows the simulation of the above mentioned stress dependence on device and circuit level. The analog circuit designer can employ the simulation technique toward the proposal of circuit topologies or techniques, which minimize or compensate the strain-induced changes on the circuit operation. In this direction, circuit concepts and design rules are proposed, which minimize the influence of mechanical stress on flexible CIS chips. Within the scope of this work, a mechanically flexible CMOS image sensor chip has been designed, simulated and fabricated, which operation is stress independent. The developed ultra-thin 20 μm CIS chip can be wrapped around a cylindrically curved surface and thus record panoramic optical information

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Electrically Controlled Reversible Strain Modulation in MoS2_2 Field-effect Transistors via an Electro-mechanically Coupled Piezoelectric Thin Film

Strain can efficiently modulate the bandgap and carrier mobilities in two-dimensional (2D) materials. Conventional mechanical strain-application methodologies that rely on flexible, patterned or nano-indented substrates are severely limited by low thermal tolerance, lack of tunability and/or poor scalability. Here, we leverage the converse piezoelectric effect to electrically generate and control strain transfer from a piezoelectric thin film to electro-mechanically coupled ultra-thin 2D MoS$_2$. Electrical bias polarity change across the piezoelectric film tunes the nature of strain transferred to MoS$_2$ from compressive $\sim$0.23% to tensile $\sim$0.14% as verified through peak shifts in Raman and photoluminescence spectroscopies and substantiated by density functional theory calculations. The device architecture, built on a silicon substrate, uniquely integrates an MoS$_2$ field-effect transistor on top of a metal-piezoelectric-metal stack enabling strain modulation of transistor drain current 130$\times$, on/off current ratio 150$\times$, and mobility 1.19$\times$ with high precision, reversibility and resolution. Large, tunable tensile (1056) and compressive (-1498) strain gauge factors, easy electrical strain modulation, high thermal tolerance and substrate compatibility make this technique promising for integration with silicon-based CMOS and micro-electro-mechanical systems.Comment: Manuscript and Supplementary Informatio

Journal of Telecommunications and Information Technology, 2001, nr 1

kwartalni

Smart Platform for Low-Cost MEMS Sensors – Pressure, Flow and Thermal Conductivity

In a technological world that is trending towards smart and autonomous engineering, the collection of quality data is of unrivalled importance. This has led to a huge market demand for the development of low-cost, small and accurate sensors and thus has resulted in significant research into sensors, with the aim of advancing the price/performance ratio in commercial solutions. Micro Electro Mechanical Systems (MEMS) have recently offered an attractive solution to miniaturise and drastically improve the performance of sensors. In this thesis, MEMS technology is exploited to create a multi-sensor technology platform that is used to fabricate several sensing technologies. Piezo-resistive and piezo-electronic pressure sensors are designed, fabricated and tested. Different doping profiles, stress-engineered structures and electronic devices for pressure transduction are investigated, with focus on their sensitivity and non-linearity. A ring is fabricated in the metal layer around the circumference of the membrane that alleviates the effects of over/under etching. This is achieved by creating a new rigid edge of the membrane in the metal layer, which has tighter fabrication tolerances. A piezo-MOSFET is developed and shown to have greater sensitivity than similar state-of-the-art devices. Flow sensors based on a heated tungsten wire are designed, fabricated, tested and substantiated with numerical modelling. Calorimetric and anemometric driving modes are optimised with regards to device structure. Thermodiodes are also used as the temperature transduction devices and are compared to the traditional resistor method and showed to be preferable when further miniaturising the sensor. Thermal conductivity gas sensors based on a heated tungsten resistor are designed, tested and substantiated with numerical modelling. Holes through the membrane are used to improve the sensitivity to measuring carbon dioxide by 270%. Asymmetric holes are utilised to prove a novel method of measuring thermal conductivity in a calorimetric method. Designs improving this new concept are outlined and substantiated with analytical and numerical models. Linear statistical methods and artificial neural networks are used to differentiate flow rate and gas concentration using three on-membrane resistors. With membrane holes, the discrimination between gases in the presence of flow is improved. Neural networks provide a viable solution and show an increase in the accuracy of both flow rate and gas concentration. The main objective of the work in this thesis was to develop low-cost, low-power, small devices capable of high-volume production and monolithic integration using a single smart technology platform for fabrication. The smart technology platform was used to create pressure sensors, flow sensors and thermal conductivity gas sensors. Within each sensing technology, proof-of-concepts and optimisations have been carried out in order to maximise performance whilst using the low-cost, high-volume fabrication process, ultimately helping towards smart and autonomous engineering solutions driven by data

Caractérisation électrique des propriétés d'interface dans les MOSFET nanométriques par des mesures de bruit basse fréquence

In this thesis, electrical properties of gate oxide/channel interface in ultra-scaled nanowire (NW) MOSFETs were experimentally investigated by carrier transport and low-frequency noise (LFN) characterizations. NW FETs, which have aggressively downscaled cross-section of the body, are strong candidates for near future CMOS node. However, the interface quality could be a critical issue due to the large surface/volume ratio, the multiple surface orientations, and additional strain technology to enhance the performance. Understanding of carrier transport and channel interface quality in NW FETs with advanced high-k/metal gate is thus particularly important. LFN provides deep insights into the interface properties of MOSFET without lower limit of required channel size. LFN measurement thus can be a powerful technique for ultra-scaled NW FETs. Also, fitting mobility (such as low-field mobility) extraction by Y-function method is an efficient method. Omega-gate NW FETs were fabricated from FD-SOI substrates, and with Hf-based high-k/metal gate (HfSiON/TiN), reducing detrimental effects by device downscaling. In addition, strain technologies to the channel were additively processed. Tensile strained-SOI substrate was used for NMOS, whereas compressive stressors were used for PMOS devices. Strained Si channel for PMOS was processed by raised SiGe S/D and CESL formations. Strained SiGe channel (SGOI) was also fabricated for further high-performance PMOS FETs. Firstly, the most common Id-Vg was characterized in single-channel NW FETs as the basic performance. Reference SOI NWs provided the excellent static control down to short channel of 17nm. Stressors dramatically enhanced on-current owing to a modification of channel energy-band structure. Then, extracted low-field mobility in NWs also showed large improvement of the performance by stressors. The mobility extraction effectively evaluated FET performance even for ultra-scaled NWs. Next, LFN investigated for various technological and architectural parameters. Carrier number fluctuations with correlated mobility fluctuations (CNF+CMF) model described 1/f noise in all our FETs down to the shortest NWs. Drain current noise behavior was basically similar in both N- and PMOS FETs regardless of technological splits. Larger 1/f noise stemming from S/D regions in PMOS FETs was perfectly interpreted by the CNF+CMF model completed with Rsd fluctuations. This observation highlighted an advantage of SGOI NW with the lowest level of S/D region noise. Geometrical variations altered the CNF component with simple impact of device scaling (reciprocal to both Wtot and Lg). No large impact of surface orientation difference between the channel (100) top and (110) side-walls in [110]-oriented NWs was observed. Scaling regularity with both Wtot and Lg, without much quantum effect, could be attributed to the use of HfSiON/TiN gate and carrier transport occurring mostly near top and side-wall surfaces even in NW geometry. Meanwhile, the CMF factor was not altered by decreasing dimensions, while the mobility strongly depends on the impact. Extracted oxide trap density was roughly steady with scaling, structure, and technological parameter impacts. Simple separation method of the contributions between channel top surface and side-walls was demonstrated in order to evaluate the difference. It revealed that oxide quality on (100) top and (110) side-walls was roughly comparable in all the [110]-devices. The density values lie in similar order as the recent reports. An excellent quality of the interface with HfSiON/TiN gate was thus sustained for all our technological and geometrical splits. Finally, our NWs fulfilled 1/f LFN requirements stated in the ITRS 2013 for future MG CMOS logic node. Consequently, we concluded that appropriate strain technologies powerfully improve both carrier transport and LFN property for future CMOS circuits consisting of NW FETs, without any large concern about the interface quality.Dans cette thèse, les propriétés électriques de transistors à nanofils de silicium liées à l'interface oxyde de grille/canal ont été étudiées par le biais de mesures de bruit basse fréquence (bruit 1/f) et de transport dans le canal. Ces transistors nanofils dont les dimensions ont été réduites jusqu'à quelques nanomètres pour la section, représentent une alternative sérieuse pour les futurs nœuds technologiques CMOS. Cependant, la qualité de l'interface oxyde de grille/canal pose question pour transistors dont l'architecture s'étend dans les 3 dimensions, en raison du fort rapport surface/volume inhérent à ces transistors, des différentes orientations cristallographiques de ces interfaces, ou encore des matériaux contraints utilisés pour améliorer les performances électriques. La compréhension des liens entre les propriétés de transport des porteurs dans le canal, qui garantissent en grande partie les performances électriques des transistors, et la qualité de l'interface avec l'oxyde de grille est fond primordiale pour optimiser les transistors nanofils. Les mesures de bruit, associées à l'étude du transport dans le canal, sont un outil puissant et adapté à ces dispositifs tridimensionnels, sans être limité par la taille ultra-réduite des transistors nanofils. Les transistors nanofils étudiés ont été fabriqués à partir de substrats minces SOI, et intègrent un empilement de grille HfSiON/TiN, qui permet de réduire les dimensions tout en conservant les mêmes propriétés électrostatiques. Pour gagner en performances, des contraintes mécaniques ont été introduites dans le canal en silicium : en tension pour les NMOS, par le biais de substrat contraint (sSOI), et en compression pour les PMOS. Un canal en compression uni-axiale peut être obtenu par l'intégration de source/drain en SiGe et/ou par l'utilisation de couches contraintes de type CESL. Des transistors à canal SiGe sur isolant en compression ont également été fabriqués et étudiés. Les caractéristiques électriques des divers transistors nanofils (courbes Id-Vg, compromis Ion-Ioff, mobilité des porteurs) démontrent l'excellent contrôle électrostatique dû à l'architecture 3D, ainsi que l'efficacité de l'ingénierie de contraintes dans les nanofils jusqu'à de faibles longueurs de grilles (~17nm). Des mesures de bruit basse fréquence ont été réalisées sur ces mêmes dispositifs et analysées en fonction des paramètres géométriques de l'architecture nanofils (largeur W, forme de la section, longueur de grille L), et des diverses variantes technologiques. Nous avons démontré que le bruit 1/f dans les transistors nanofils peut être décrit par le modèle de fluctuations du nombre de porteurs (CNF) corrélées aux fluctuations de mobilité (CMF). Le bruit associé aux régions S/D a pu également être intégré dans ce modèle en ajoutant une contribution, en particulier pour les PMOS. Alors que les différentes variantes technologiques ont peu d'effet sur le bruit 1/f, les variations de géométrie en L et W changent la composante de bruit liée aux fluctuations du nombre de porteurs (CNF) de manière inversement proportionnelle à la surface totale (~1/WL). Cette augmentation du bruit est le reflet du transport qui se produit à proximité des interfaces avec l'oxyde. Les différentes orientations des interfaces supérieures et latérales (110) ou (100) présentent la même quantité de pièges d'interface (extrait à partir des mesures de bruit 1/f, en séparant les contributions des différentes faces du nanofil) bien qu'ayant une rugosité différente essentiellement liée au process. En revanche la composante CMF n'est pas altérée par la réduction des dimensions contrairement à la mobilité des porteurs qui décroit fortement avec L. Finalement, les mesures de bruit 1/f ont été comparées aux spécifications ITRS 2013 pour les transistors multi-grilles en vue des futurs nœuds technologiques de la logique CMOS, et démontrent que nos transistors nanofils satisfont les exigences en la matière

Strain integration and performance optimization in sub-20nm FDSOI CMOS technology

La technologie CMOS à base de Silicium complètement déserté sur isolant (FDSOI) est considérée comme une option privilégiée pour les applications à faible consommation telles que les applications mobiles ou les objets connectés. Elle doit cela à son architecture garantissant un excellent comportement électrostatique des transistors ainsi qu'à l'intégration de canaux contraints améliorant la mobilité des porteurs. Ce travail de thèse explore des solutions innovantes en FDSOI pour nœuds 20nm et en deçà, comprenant l'ingénierie de la contrainte mécanique à travers des études sur les matériaux, les dispositifs, les procédés d'intégration et les dessins des circuits. Des simulations mécaniques, caractérisations physiques (µRaman), et intégrations expérimentales de canaux contraints (sSOI, SiGe) ou de procédés générant de la contrainte (nitrure, fluage de l'oxyde enterré) nous permettent d'apporter des recommandations pour la technologie et le dessin physique des transistors en FDSOI. Dans ce travail de thèse, nous avons étudié le transport dans les dispositifs à canal court, ce qui nous a amené à proposer une méthode originale pour extraire simultanément la mobilité des porteurs et la résistance d'accès. Nous mettons ainsi en évidence la sensibilité de la résistance d'accès à la contrainte que ce soit pour des transistors FDSOI ou nanofils. Nous mettons en évidence et modélisons la relaxation de la contrainte dans le SiGe apparaissant lors de la gravure des motifs et causant des effets géométriques (LLE) dans les technologies FDSOI avancées. Nous proposons des solutions de type dessin ainsi que des solutions technologiques afin d'améliorer la performance des cellules standard digitales et de mémoire vive statique (SRAM). En particulier, nous démontrons l'efficacité d'une isolation duale pour la gestion de la contrainte et l'extension de la capacité de polarisation arrière, qui un atout majeur de la technologie FDSOI. Enfin, la technologie 3D séquentielle rend possible la polarisation arrière en régime dynamique, à travers une co-optimisation dessin/technologie (DTCO).The Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization