Coupling Inductor Based Hybrid Millimeter-Wave Switch

A switch comprising a plurality of inductors and a plurality of shunt transistors is described. Each inductor can be electrically coupled between adjacent shunt transistors to form a distributed switch structure. At least two inductors in the plurality of inductors can be inductively coupled with each other. The plurality of inductors can correspond to portions of a coupling inductor, wherein the coupling inductor can have an irregular octagonal shape

CMOS Front-End Circuits in 45-nm SOI Suitable for Modular Phased-Array 60-GHz Radios

Next Fifth-generation (5G) wireless technologies enabling ultra-wideband spectrum availability and increased system capacity can achieve multi-gigabit/s (Gbps) data rates suitable for ultra-high-speed internet access around the 60-GHz band (i.e., Wi-Gig Technology). This mm-wave band is unlicensed and experiences high propagation power losses. Therefore, it is suitable for short-range communications and requires antenna arrays to satisfy the link budget requirements. Half-duplex reconfigurable phased-array transceivers require wideband, low-cost, highly integrated front-end circuits such as bilateral RF switches, low-noise/power amplifiers, passive RF splitters/combiners, and phase shifters implemented in deep sub-micron CMOS. In this dissertation, analysis, design, and verification of essential CMOS front-end components are covered and fabricated in GlobalFoundries 45-nm RF-SOI CMOS technology. Firstly, a fully-differential, single-pole, single-throw (SPST) switch capable of high isolation in broadband CMOS transceivers is described. The SPST switch realizes better than 50-dB isolation (ISO) across DC to 43 GHz while maintaining an insertion loss (IL) below 3 dB. Measured RF input power for 1-dB compression (IP1dB) of the IL is +19.6 dBm, and the measured input third-order intercept point (IIP3) is +30.4 dBm (both assuming differential inputs at 20 GHz). The prototype has an active area of 0.0058 mm^2. Secondly, a single-pole double-throw (SPDT) switch is implemented using the SPST concept by using a balun to convert the shared differential path to a single-ended antenna port. The SPDT simulations predict less than 3.5-dB IL and greater than 40-dB ISO across 55 to 65 GHz frequency band. An IP1dB of +21 dBm is expected from large-signal simulations. The prototype has an active area of 0.117 mm^2. Thirdly, a fully-differential switched-LC topology adopted with slow-wave artificial transmission line concept, and phase inversion network is described for a 360-degree phase shift range with 11.25-degree phase resolution. The average IL of the complete phase shifter is 5.3 dB with less than 1-dB rms IL error. Furthermore, the IP1dB of the phase shifter is +16 dBm. The prototype has an active area of 0.245 mm^2. Lastly, a fully-differential, 2-stage, common-source (CS) low-noise amplifier (LNA) is developed with wideband matching from 57.8 GHz to 67 GHz, a maximum simulated forward power gain of 20.8 dB, and a minimum noise figure of 3.07 dB. The LNA consumes 21 mW and predicts an OP1dB of 4.8 dBm from the 1-V supply. The LNA consumes an active area of 0.028 mm^2

Millimeter-Wave Reconfigurable CMOS-MEMS Integrated Devices

The millimeter-wave spectrum has sparked interest recently as a promising alternative to meet bandwidth requirements for wireless local area networks, vehicular radars, short-range multi-Gb/s links, and next-generation cellular system communications (5G). The unlicensed 7 GHz ISM band around 60 GHz is of particular interest. Compared to semiconductor technologies, Micro-Electro-Mechanical Systems (MEMS) have the potential to realize reconfigurable millimeter-wave devices with superior performance in terms of linearity, insertion loss and DC power consumption. This thesis presents the development and fabrication of miniaturized, low insertion loss, high isolation RF-MEMS switches implemented in CMOS chips through the use of a post-processing technique. Several CMOS-MEMS switches operating at 60 GHz and 77 GHz are demonstrated. Prototype units for SPST, SP3T switches and a distributed MEMS transmission line (DMTL) network are integrated on CMOS 0.35 μm. The challenges involved in realizing CMOS-MEMS devices at mm-wave frequencies are also addressed in this work

SiGe/CMOS Millimeter-Wave Integrated Circuits and Wafer-Scale Packaging for Phased Array Systems.

Phased array systems have been used to achieve electronic beam control and fast beam scanning. In the RF-phase shifting architecture, T/R modules are required for each antenna element, and have been traditionally developed using GaAs or InP technology. This thesis demonstrates that Ka-band (35 GHz) T/R modules can also be developed using the SiGe BiCMOS technology. The designed circuit blocks include a low noise amplifier, a 4-bit phase shifter, a variable gain amplifier/attenuator, and SPDT switches. The Ka-band phase shifters are designed based on CMOS switch and miniature low-pass networks for a single-ended and differential applications, and result in 3-degree rms phase error at 35 GHz. The SiGe LNA results in a peak gain of 24 dB and a noise figure of 2.9-3.1 dB with 11 mW power consumption. The CMOS variablestep attenuator has 12-dB attenuation range (1 dB step) with very low loss and phase imbalance at 10-50 GHz. A variable gain LNA is also demonstrated at 30-40 GHz for the differential phased array receiver, and has 20-dB gain and <1-degree rms phase imbalance between the 8 different gain states and 10 dB gain control. All of these circuits show state-of-the-art performance, and the phase shifter, distributed attenuator and VGA are also first-time demonstrations at Ka-band frequencies. These circuit blocks were used in a miniature SiGe/CMOS Ka-band T/R module with a dimension of 0.93x1.33mm2, and a measured performance of 19 dB receive gain, 4-5 dB NF, 9 dB transmit gain and +5.5 dBm output P1dB. The T/R module also has 4-bit phase control and 10 dB gain control in both the transmit and receive modes. To our knowledge, this is the first demonstration of a Ka-band SiGe/CMOS T/R module to-date. Finally, a DC-110 GHz Si wafer-scale packaging technique has been developed using thermo-compression bonding and is suitable for Ka-band and even W-band T/R modules. The package transition has an insertion loss of 0.1-0.26 dB at 30-110 GHz, and the package resonances and leakage were drastically reduced by grounding the sealing ring. This is the first demonstration of a wideband resonance-free (DC-110 GHz) package using silicon technology.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58380/1/bmin_1.pd

Reconfigurable high efficiency class-F power amplifier using CMOS-MEMS technology

The increasing demand for wireless products to be part of our daily lives brings the need for longer battery lifetime, smaller size and lower cost. To increase battery lifetime, high efficiency power amplifiers (PAs) are needed; To make them smaller, integration or reconfiguration is aimed and to reach lower costs, technologies such as CMOS are final goals. However integration of high efficiency PA in CMOS is challenging due to the technology limitations which restricts the achievable output power and efficiency of the PA. In order to bring solutions for the above-mentioned requirements, in this thesis novel reconfigurable class-F PAs, frequency-reconfiguration, CMOS integration, impedance-reconfiguration and CMOS-MEMS implementation are addressed. Starting with a single frequency operation, a novel class-F PA for mobile applications is proposed in which with a proper harmonic tuning structure the need for extra filtering sections is eliminated, achieving an excellent harmonic-suppression level. This topology uses transmission lines and is developed to cover multiple frequency bands for purpose of global coverage with aim of size reduction. Three novel frequency reconfigurable PAs are proposed using MEMS and semiconductor switches to accomplish class-F operation at two frequencies. The main novelty of this structure is that the reconfiguration is done not only at fundamental frequency but also at harmonics with reduced number of tuning elements. Moreover, by proper placement of the switches in the stubs, the maximum voltages over the switches are minimized. The proposed structure overcomes the narrow band performance of class-F, giving an efficiency more than 60% over a 225 MHz and 175 MHz bandwidth at 900 MHz and 1800 MHz respectively. Measurement results showed high performance at both frequency bands giving 69.5% and 57.9% PAE at 900 MHz and 1800 MHz respectively. A novel CMOS class-F PA is proposed that controls up to the 3rd harmonic and can adapt to load variations due to the effect of the human body on mobile phones. It enables the integration of the PA with other devices in a single chip leading to better matching, higher performance, lower cost and smaller size. In addition, it achieves load impedance reconfigurability by using impedance tuner in its output network and by proper tuning of the network, effects of load variation on the performance are compensated. Two designs at 2.4 GHz have been done using either MOS varactors or MEMS variable capacitors as tuning devices. The design using MOS varactors show a maximum measured values of 26% PAE and 19.2 dBm output power for 50 load. For loads other than 50 ohm an improvement of 15% for PAE and 4.4 dB for output power is obtained in comparison to non-tuned one. The second design is done using MEMS variable capacitors integrated in CMOS technology through a mask-less post-processing technique. Simulations results for 50 ohm load show a peak PAE of 32.8% while delivering 18.2 dBm output power.La creixent demanda de productes sense fils en la nostra vida diària requereix dispositius de menor grandària, menor cost i amb una gran autonomia. Per reduir la mida i augmentar l'autonomia és necessari utilitzar sistemes integrats multiestàndard o reconfigurables, amb amplificadors de RF d'alta eficiència, mentre que per reduir el cost, és preferible utilitzar tecnologies econòmiques com CMOS. No obstant això, la integració en CMOS d'amplificadors de radiofreqüència, i en especial, d'alta eficiència, és un repte a causa de les limitacions de la tecnologia que restringeixen la potència de sortida realitzable i l'eficiència de l'amplificador. En aquesta tesi es tracten els diferents reptes anteriorment esmentats, proposant una nova topologia d'amplificador classe-F amb reconfiguració de freqüència, i proposant la integració d'un amplificador classe-F que s¿adapta a impedància de càrrega variable, implementat en CMOS i CMOS-MEMS. Inicialment en la tesi es proposa una topologia d'amplificador classe-F en què, gràcies a una estructura adequada a la xarxa d'adaptació, s¿elimina la necessitat de filtrat extra, aconseguint un nivell de rebuig d'harmònics excel·lent. La topologia proposada utilitza línies de transmissió i s'ha desenvolupat per dues bandes diferents, amb el disseny orientat a implementar un sistema reconfigurable. S'han aconseguit PAE de l'ordre del 80 % amb potències properes a 10 W. Un cop descrita i analitzada la topologia, s'han proposat tres amplificadors reconfigurables per doble banda freqüencial. Per a la reconfiguració s'han utilitzat MEMS i commutadors basats en semiconductors. L'estructura proposada permet la reconfiguració no només en la freqüència fonamental sinó també en els harmònics, però mantenint un nombre reduït d'elements d'ajust. A més, gràcies a l'adequada col·locació dels commutadors en les línies de transmissió, s'ha minimitzat la tensió màxima en els mateixos. Així mateix, l'estructura proposada evita la característica de banda estreta a classe-F, proporcionant una eficiència superior al 60% en unes amplades de banda de 225 MHz i de 175 MHz, per a les banda de 900 MHz i 1800 MHz respectivament. En aquestes bandes, la PAE màxima mesurada és del 69,5% i del 57,9% respectivament. Finalment, s'ha proposat un amplificador integrat en CMOS, classe-F amb control fins al tercer harmònic. L'amplificador proposat incorpora un sintonitzador a la sortida, podent així adaptar-se a variacions d'impedància de càrrega, típiques en dispositius sense fil (WLAN), degudes a l'efecte del cos humà sobre l'antena. La implementació en CMOS permet la integració de l'amplificador de potència amb altres dispositius en un únic xip, donant lloc a una millor adaptació, millor rendiment, menor cost i menor grandària del sistema. A més, gràcies a l'adaptació a les variacions de la impedància de càrrega, permet mantenir el rendiment en diferents rangs d'operació. S'han realitzat dos dissenys de l'amplificador a 2,4 GHz, un basat en varactors MOS i un altre en condensadors variables MEMS. El disseny que utilitza varactors MOS mostra una PAE màxima del 26% i una potència de 19,2 dBm per a càrrega adaptada 50 ohm. Per altres càrregues, gràcies a l'adaptació d'impedància, s'obté una millora de PAE del 15% i de 4,4 dB en potència de sortida. El disseny utilitzant condensadors MEMS s'integra en CMOS gràcies a post-processat sense màscares addicionals. Els resultats de simulació per a 50 ohm mostren una PAE del 32,8% per 18,2 dBm de potència de sortid

Compact Millimeter-Wave Bandpass Filters Using Quasi-Lumped Elements in 0.13-um (Bi)-CMOS Technology for 5G Wireless Systems

© 2019 IEEE.A design methodology for a compact millimeter-wave on-chip bandpass filter (BPF) is presented in this paper. Unlike the previously published works in the literature, the presented method is based on quasi-lumped elements, which consists of a resonator with enhanced self-coupling and metal-insulator-metal capacitors. Thus, this approach provides inherently compact designs comparing with the conventional distributed elements-based ones. To fully understand the insight of the approach, simplified LC-equivalent circuit models are developed. To further demonstrate the feasibility of using this approach in practice, the resonator and two compact BPFs are designed using the presented models. All three designs are fabricated in a standard 0.13- \mu \text{m} (Bi)-CMOS technology. The measured results show that the resonator can generate a notch at 47 GHz with the attenuation better than 28 dB due to the enhanced self-coupling. The chip size, excluding the pads, is only 0.096 \times 0.294 mm 2. In addition, using the resonator for BPF designs, the first BPF has one transmission zero at 58 GHz with a peak attenuation of 23 dB. The center frequency of this filter is 27 GHz with an insertion loss of 2.5 dB, while the return loss is better than 10 dB from 26 to 31 GHz. The second BPF has two transmission zeros, and a minimum insertion loss of 3.5 dB is found at 29 GHz, while the return loss is better than 10 dB from 26 GHz to 34 GHz. Also, more than 20-dB stopband attenuation is achieved from dc to 20.5 GHz and from 48 to 67 GHz. The chip sizes of these two BPFs, excluding the pads, are only 0.076\times 0.296 mm 2 and 0.096\times 0.296 mm 2, respectively.Peer reviewe

RF-MEMS Switch Module in a 0.25 µm SiGe:C BiCMOS Process

Drahtlose Kommunikationstechnologien im Frequenzbereich bis 6 GHz wurden in der Vergangenheit in Bezug auf Leistungsfaehigkeit und Frequenzbereich kontinuierlich verbessert. Aufgrund der Skalierung nach dem Mooreschen Gesetz koennen heutzutage mm-Wellen Schaltkreise in CMOS-Technologien hergestellt werden. Durch die Einfuehrung von SiGe zur Realisierung einer leistungsfaehigen BiCMOS-Technologie wurde ebenfalls eine Verbesserung der Frequenzeigenschaften und Ausgangsleistungen erreicht, wodurch aktive CMOS- oder BiCMOS-Bauelemente vergleichbare Leistungsparameter zu III-V Technologien bei geringeren Kosten bereitstellen koennen. Bedingt durch das niederohmige Silizium-Substrat der BiCMOS-Technologie weisen vor allem passive Komponenten hoehere Verluste auf und weder III-V- noch BiCMOS-Technologien bieten hochlineare Schaltkomponenten mit geringen Verlusten und geringen Leistungsaufnahmen im mm-Wellen Bereich. RF-MEMS Schalter sind bekannt fuer ihre ausgezeichneten HF-Eigenschaften. Die Leistungsaufnahme von elektrostatisch angetriebenen RF-MEMS Schaltern ist vernachlaessigbar und es koennen im Vergleich zu halbleiter-basierten Schaltern hoehere Leistungen verarbeitet werden. Nichtsdestotrotz wurden RF-MEMS Schalter hauptsaechlich als eigenstaendige Komponenten entwickelt. Zur Systemintegration wird meist ein System-in-Package (SiP) Ansatz angewandt, der fuer niedrige Frequenzen geeignet ist, aber bei mm-Wellenanwendungen durch parasitaere Verluste an seine Grenzen stoesst. In dieser Arbeit wird ein in eine BiCMOS-Technologie integrierter RF-MEMS Schalter fuer mm-Wellen Anwendungen gezeigt. Das Design, die Integration und die experimentellen Ergebnisse sowie verschiedene Packaging-Konzepte werden beschrieben Zur Bereitstellung der hohen Auslenkungs-Spannungen wurde eine Ladungspumpe auf dem Chip integriert. Zum Schluss werden verschiedene, rekonfigurierbare mm-Wellen Schaltkreise zur Demonstration der Leistungsfaehigkeit des Schalters gezeigt.Wireless communication technologies have continuously advanced for both performance and frequency aspects, mainly for the frequencies up to 6 GHz. The results of Moore’s law now also give the opportunity to design mm-wave circuits using advanced CMOS technologies. The introduction of SiGe into CMOS, providing high performance BiCMOS, has also enhanced both the frequency and the power performance figures. The current situation is that the active devices of both CMOS and BiCMOS technologies can provide performance figures competitive with III-V technologies while having still the advantage of low cost. However, similar competition cannot be pronounced for the passive components considering the low-resistive substrates of BiCMOS technologies. Moreover, both III-V and BiCMOS technologies have the lack of low-loss and low-power consumption, as well as highly linear switching and tuning components at mm-wave frequencies. RF-MEMS switch technologies have been well-known with excellent RF- performance figures. The power consumption of electrostatic RF-MEMS switches is negligible and they can handle higher power levels compared to their semiconductor counterparts. However, RF-MEMS switches have been mostly demonstrated as standalone processes and have started to be used as commercial off-the-shelf (COTS) devices recently. The full system integration is typically done by a System-in-Package (SiP) approach. Although SiP is suitable for lower frequencies, the packaging parasitics limit the use of this approach for the mm-wave frequencies. In this thesis, a fully BiCMOS embedded RF-MEMS switch for mm-wave applications is proposed. The design, the implementation and the experimental results of the switch are provided. The developed RF-MEMS switch is packaged using different packaging approaches. To actuate the RF-MEMS switch, an on-chip high voltage generation circuit is designed and characterized. The robustness and the reliability performance of the switch are also presented. Finally, the developed RF-MEMS switch is successfully demonstrated in re-configurable mm-wave circuits

Millimeter-Wave Concurrent Dual-Band Sige Bicmos Rfic Phased-Array Transmitter and Components

A concurrent dual-band phased-array transmitter (TX) and its constituent components are studied in this dissertation. The TX and components are designed for the unlicensed bands, 22–29 and 57–64 GHz, using a 0.18-μm BiCMOS technology. Various studies have been done to design the components, which are suitable for the concurrent dual-band phased-array TX. The designed and developed components in this study are an attenuator, switch, phase shifter, power amplifier and power divider. Attenuators play a key role in tailoring main beam and side-lobe patterns in a phased-array TX. To perform the function in the concurrent dual-band phased-array TX, a 22–29 and 57–64 GHz concurrent dual-band attenuator with low phase variations is designed. Signal detection paths are employed at the output of the phased-array TX to monitor the phase and amplitude deviations/errors, which are larger in the high-frequency design. The detected information enables the TX to have an accurate beam tailoring and steering. A 10–67 GHz wide-band attenuator, covering the dual bands, is designed to manipulate the amplitude of the detected signal. New design techniques for an attenuator with a wide attenuation range and improved flatness are proposed. Also, a topology of dual-function circuit, attenuation and switching, is proposed. The switching turns on and off the detection path to minimize the leakages while the path is not used. Switches are used to minimize the number of components in the phased-array transceiver. With the switches, some of the bi-directional components in the transceiver such as an attenuator, phase shifter, filter, and antenna can be shared by the TX and receiver (RX) parts. In this dissertation, a high-isolation switch with a band-pass filtering response is proposed. The band-pass filtering response suppresses the undesired harmonics and intermodulation products of the TX. Phase shifters are used in phased-array TXs to steer the direction of the beam. A 24-GHz phase shifter with low insertion loss variation is designed using a transistor-body-floating technique for our phased-array TX. The low insertion loss variation minimizes the interference in the amplitude control operation (by attenuator or variable gain amplifier) in phased-array systems. BJTs in a BiCMOS process are characterized across dc to 67 GHz. A novel characterization technique, using on-wafer calibration and EM-based de-embedding both, is proposed and its accuracy at high frequencies is verified. The characterized BJT is used in designing the amplifiers in the phased-array TX. A concurrent dual-band power amplifier (PA) centered at 24 and 60 GHz is proposed and designed for the dual-band phased-array TX. Since the PA is operating in the dual frequency bands simultaneously, significant linearity issues occur. To resolve the problems, a study to find significant intermodulation (IM) products, which increase the third intermodulation (IM3) products most, has been done. Also, an advanced simulation and measurement methodology using three fundamental tones is proposed. An 8-way power divider with dual-band frequency response of 22–29 and 57–64 GHz is designed as a constituent component of the phased-array TX

CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers

Ultra-wideband technology (UWB) has received tremendous attention since the FCC license release in 2002, which expedited the research and development of UWB technologies on consumer products. The applications of UWB range from ground penetrating radar, distance sensor, through wall radar to high speed, short distance communications. The CMOS integrated circuit is an attractive, low cost approach for implementing UWB technology. The improving cut-off frequency of the transistor in CMOS process makes the CMOS circuit capable of handling signal at multi-giga herz. However, some design challenges still remain to be solved. Unlike regular narrow band signal, the UWB signal is discrete pulse instead of continuous wave (CW), which results in the occupancy of wide frequency range. This demands that UWB front-end circuits deliver both time domain and frequency domain signal processing over broad bandwidth. Witnessing these technique challenges, this dissertation aims at designing novel, high performance components for UWB signal generation, down-conversion, as well as accurate timing control using low cost CMOS technology. We proposed, designed and fabricated a carrier based UWB transmitter to facilitate the discrete feature of the UWB signal. The transmitter employs novel twostage -switching to generate carrier based UWB signal. The structure not only minimizes the current consumption but also eliminates the use of a UWB power amplifier. The fabricated transmitter is capable of delivering tunable UWB signal over the complete 3.1GHz -10.6GHz UWB band. By applying the similar two-stage switching approach, we were able to implement a novel switched-LNA based UWB sampling receiver frontend. The proposed front-end has significantly lower power consumption compared to previously published design while keep relatively high gain and low noise at the same time. The designed sampling mixer shows unprecedented performance of 9-12dB voltage conversion gain, 16-25dB noise figure, and power consumption of only 21.6mW(with buffer) and 11.7mW(without buffer) across dc to 3.5GHz with 100M-Hz sampling frequency. The implementation of a precise delay generator is also presented in the dissertation. It relies on an external reference clock to provide accurate timing against process, supply voltage and temperature variation through a negative feedback loop. The delay generator prototype has been verified having digital programmability and tunable delay step resolution. The relative delay shift from desired value is limited to within 0.2%

Radio Frequency and Millimeter Wave Circuit Component Design with SiGe BiCMOS Technology

The objective of this research is to study and leverage the unique properties and advantages of silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) integrated circuit technologies to better design radio frequency (RF) and millimeter wave (mm-wave) circuit components. With recent developments, the high yield and modest cost silicon-based semiconductor technologies have proven to be attractive and cost-effective alternatives to high-performance III-V technology platforms. Between SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology and advanced RF complementary metal-oxide-semiconductor (CMOS) technology, the fundamental device-level differences between SiGe HBTs and field-effect transistors (FETs) grant SiGe HBTs clear advantages as well as unique design concerns. The work presented in this dissertation identifies several advantages and challenges on design using SiGe HBTs and provides design examples that exploit and address these unique benefits and problems with circuit component designs using SiGe HBTs.Ph.D