829 research outputs found
Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements
The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver
A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-”m SiGe BiCMOS for Radar and Communication Systems
Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems.
A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emittersâ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86Âș, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems.
The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption
A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-”m SiGe BiCMOS for Radar and Communication Systems
Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems.
A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emittersâ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86Âș, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems.
The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption
Programmable rate modem utilizing digital signal processing techniques
The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery
Design and Implementation of an RF Front-End for Software Defined Radios
Software Defined Radios have brought a major reformation in the design standards for radios, in which a large portion of the functionality is implemented through pro grammable signal processing devices, giving the radio the ability to change its op erating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency and other analog components of the traditional radios and emphasizes digital signal processing to enhance overall receiver flexibility. Field Programmable Gate Arrays (FPGA) are a suitable technology for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability.
Software defined radio is a very broad field, encompassing the design of various technologies all the way from the antenna to RF, IF, and baseband digital design. The RF section primarily consists of analog hardware modules. The IF and baseband sections are primarily digital. It is the general process of the radio to convert the incoming signal from RF to IF and then IF to baseband for better signal processing system.
In this thesis, some of major building blocks of a Software defined radio are de signed and implemented using FPGAs. The design of a Digital front end, which provides the bridge between the baseband and analog RF portions of a wireless receiver, is synthesized. The Digital front end receiver consists of a digital down converter(DDC) which in turn comprises of a direct digital frequency synthesizer (DDFS), a phase accumulator and a low pass filter. The signal processing block
of the DDFS is executed using Co-ordinate Rotation Digital Computer (CORDIC) iii
Abstract
algorithm. Cascaded-Integrator-Comb filters (CIC) are implemented for changing the sample rate of the incoming data. Application of a DDC includes software ra dios, multicarrier, multimode digital receivers, micro and pico cell systems,broadband data applications, instrumentation and test equipment and in-building wireless tele phony. Also, in this thesis, interfaces for connecting Texas Instruments high speed and high resolution Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) with Xilinx Virtex-5 FPGAs are also implemented and demonstrated
An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers
Dissertação apresentada na faculdade de CiĂȘncias e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia ElectrotĂ©cnica e de ComputadoresThe rapid growth of wireless communications and the massive use of wireless end-user
equipments have created a demand for low-cost, low-power and low-area devices with
tight specifications imposed by standards. The advances in CMOS technology allows,
nowadays, designers to implement circuits that work at high-frequencies, thus, allowing
the complete implementation of RF front ends in a single chip.
In this work, a co-design strategy for the implementation of a fully integrated CMOS
receiver for use in the ISM band is presented. The main focus is given to the Mixer and
the ADC blocks of the presented architecture.
The traditional approach used in RF design requires 50
matching buffers and networks
and AC coupling capacitors between Mixer inputs and LNA and LO outputs. The codesign
strategy avoids the use of DC choke inductors for Mixer biasing, because it is
possible to use the DC level from the output of the LNA and the LO to provide bias to
the Mixer. Moreover, since the entire circuit is in the same chip and the Mixer inputs
are transistors gates, we should consider voltage instead of power and avoid the 50
matching networks.
The proposed ADC architecture relies on a 4-bit flash converter. The main goals are to
achieve low-power and high sampling frequency. To meet these goals, parametric amplification
based on MOS varactors is applied to reduce the offset voltage of the comparators,
avoiding the traditional and power-consuming approach of active pre-amplification gain
stages
Dirty RF Signal Processing for Mitigation of Receiver Front-end Non-linearity
ï»żModerne drahtlose Kommunikationssysteme stellen hohe und teilweise
gegensÀtzliche Anforderungen an die Hardware der Funkmodule, wie z.B.
niedriger Energieverbrauch, groĂe Bandbreite und hohe LinearitĂ€t. Die
GewÀhrleistung einer ausreichenden LinearitÀt ist, neben anderen analogen
Parametern, eine Herausforderung im praktischen Design der Funkmodule. Der
Fokus der Dissertation liegt auf breitbandigen HF-Frontends fĂŒr
Software-konfigurierbare Funkmodule, die seit einigen Jahren kommerziell
verfĂŒgbar sind. Die praktischen Herausforderungen und Grenzen solcher
flexiblen Funkmodule offenbaren sich vor allem im realen Experiment. Eines
der Hauptprobleme ist die Sicherstellung einer ausreichenden analogen
Performanz ĂŒber einen weiten Frequenzbereich. Aus einer Vielzahl an
analogen Störeffekten behandelt die Arbeit die Analyse und Minderung von
NichtlinearitÀten in EmpfÀngern mit direkt-umsetzender Architektur. Im
Vordergrund stehen dabei Signalverarbeitungsstrategien zur Minderung
nichtlinear verursachter Interferenz - ein Algorithmus, der besser unter
"Dirty RF"-Techniken bekannt ist. Ein digitales Verfahren nach der
VorwÀrtskopplung wird durch intensive Simulationen, Messungen und
Implementierung in realer Hardware verifiziert. Um die LĂŒcken zwischen
Theorie und praktischer Anwendbarkeit zu schlieĂen und das Verfahren in
reale Funkmodule zu integrieren, werden verschiedene Untersuchungen
durchgefĂŒhrt. Hierzu wird ein erweitertes Verhaltensmodell entwickelt, das
die Struktur direkt-umsetzender EmpfÀnger am besten nachbildet und damit
alle Verzerrungen im HF- und Basisband erfasst. DarĂŒber hinaus wird die
LeistungsfÀhigkeit des Algorithmus unter realen Funkkanal-Bedingungen
untersucht. ZusÀtzlich folgt die Vorstellung einer ressourceneffizienten
Echtzeit-Implementierung des Verfahrens auf einem FPGA. AbschlieĂend
diskutiert die Arbeit verschiedene Anwendungsfelder, darunter spektrales
Sensing, robuster GSM-Empfang und GSM-basiertes Passivradar. Es wird
gezeigt, dass nichtlineare Verzerrungen erfolgreich in der digitalen
DomÀne gemindert werden können, wodurch die Bitfehlerrate gestörter
modulierter Signale sinkt und der Anteil nichtlinear verursachter
Interferenz minimiert wird. SchlieĂlich kann durch das Verfahren die
effektive LinearitÀt des HF-Frontends stark erhöht werden. Damit wird der
zuverlÀssige Betrieb eines einfachen Funkmoduls unter dem Einfluss der
EmpfÀngernichtlinearitÀt möglich. Aufgrund des flexiblen Designs ist der
Algorithmus fĂŒr breitbandige EmpfĂ€nger universal einsetzbar und ist nicht
auf Software-konfigurierbare Funkmodule beschrÀnkt.Today's wireless communication systems place high requirements on the
radio's hardware that are largely mutually exclusive, such as low power
consumption, wide bandwidth, and high linearity. Achieving a sufficient
linearity, among other analogue characteristics, is a challenging issue in
practical transceiver design. The focus of this thesis is on wideband
receiver RF front-ends for software defined radio technology, which became
commercially available in the recent years. Practical challenges and
limitations are being revealed in real-world experiments with these radios.
One of the main problems is to ensure a sufficient RF performance of the
front-end over a wide bandwidth. The thesis covers the analysis and
mitigation of receiver non-linearity of typical direct-conversion receiver
architectures, among other RF impairments. The main focus is on DSP-based
algorithms for mitigating non-linearly induced interference, an approach
also known as "Dirty RF" signal processing techniques. The conceived
digital feedforward mitigation algorithm is verified through extensive
simulations, RF measurements, and implementation in real hardware. Various
studies are carried out that bridge the gap between theory and practical
applicability of this approach, especially with the aim of integrating that
technique into real devices. To this end, an advanced baseband behavioural
model is developed that matches to direct-conversion receiver architectures
as close as possible, and thus considers all generated distortions at RF
and baseband. In addition, the algorithm's performance is verified under
challenging fading conditions. Moreover, the thesis presents a
resource-efficient real-time implementation of the proposed solution on an
FPGA. Finally, different use cases are covered in the thesis that includes
spectrum monitoring or sensing, GSM downlink reception, and GSM-based
passive radar. It is shown that non-linear distortions can be successfully
mitigated at system level in the digital domain, thereby decreasing the bit
error rate of distorted modulated signals and reducing the amount of
non-linearly induced interference. Finally, the effective linearity of the
front-end is increased substantially. Thus, the proper operation of a
low-cost radio under presence of receiver non-linearity is possible. Due to
the flexible design, the algorithm is generally applicable for wideband
receivers and is not restricted to software defined radios
Clock Generation Design for Continuous-Time Sigma-Delta Analog-To-Digital Converter in Communication Systems
Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (ÎŁÎ) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass ÎŁÎ which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system.
Clock generation, a major building block in radio frequency (RF) integrated circuits (ICs), usually uses a phase-locked loop (PLL) to provide the required clock frequency to modulate/demodulate the informative signals. This work explores the design of clock generation in RF ICs. First, a 2-16 GHz frequency synthesizer is proposed to provide the sampling clocks for a programmable continuous-time bandpass sigma-delta (ÎŁÎ) modulator in a software radio receiver system. In the frequency synthesizer, a single-sideband mixer combines feed-forward and regenerative mixing techniques to achieve the wide frequency range. Furthermore, to optimize the excess loop delay in the wideband system, a phase-tunable clock distribution network and a clock-controlled quantizer are proposed. Also, the false locking of regenerative mixing is solved by controlling the self-oscillation frequency of the CML divider. The proposed frequency synthesizer performs excellent jitter performance and efficient power consumption.
Phase noise and quadrature phase accuracy are the common tradeoff in a quadrature voltage-controlled oscillator. A larger coupling ratio is preferred to obtain good phase accuracy but suffer phase noise performance. To address these fundamental trade-offs, a phasor-based analysis is used to explain bi-modal oscillation and compute the quadrature phase errors given by inevitable mismatches of components. Also, the ISF is used to estimate the noise contribution of each major noise source. A CSD QVCO is first proposed to eliminate the undesired bi-modal oscillation and enhance the quadrature phase accuracy. The second work presents a DCC QVCO. The sophisticated dynamic current-clipping coupling network reduces injecting noise into LC tank at most vulnerable timings (zero crossing points). Hence, it allows the use of strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed DCC QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1MHz offset from a 5GHz carrier. The QVCO consumes 4.2mW with a 1-V power supply, resulting in an outstanding Figure of Merit (FoM) of 189 dBc/Hz.
Frequency divider is one of the most power hungry building blocks in a PLL-based frequency synthesizer. The complementary injection-locked frequency divider is proposed to be a low-power solution. With the complimentary injection schemes, the dividers can realize both even and odd division modulus, performing a more than 100% locking range to overcome the PVT variation. The proposed dividers feature excellent phase noise. They can be used for multiple-phase generation, programmable phase-switching frequency dividers, and phase-skewing circuits
- âŠ