A 65nm continuous-time sigma-delta modulator with limited OTA DC gain compensation

This paper explores the effects of compensating the performance degradation in high-speed Continuous-Time Sigma-Delta modulators when the loop integrators are implemented through limited gain Operational Transconductance Amplifiers. Yet, the low DC-gain strongly affects both integrator magnitude and phase responses, with a reduction in the overall effective number of bits. This work models the degradation as due to a signal-dependent memory-less perturbation and theoretically studies its compensation by feeding an opposite signal back to the integrator input. The implementation and experimental results on a 65nm CMOS 2nd order prototype evaluate the performance increase with this technique, where no other compensation, nor any digital calibration, is included. Tested in different conditions, the compensated prototype improves more than 1.5 bit the ENoB with respect to the uncompensated counterpart. For a sampling frequency of 500 MHz the power consumption is 1.7mW, resulting in a 477.2fJ/conv-lev Walden and a 148.8dB Schreirer Figures of Merit

Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC

Continuous-time filters are critical components in the implementation of large bandwidth, high frequency, and high resolution continuous-time (CT) sigma-delta (ΣΔ) analog-to-digital converters (ADCs). The loop filter defines the noise-transfer function (NTF) and hence the quantization noise-shaping behavior of the ΣΔ modulator, and becomes the most critical performance determining part in ΣΔ ADC. This thesis work presents the design considerations for the loop filter in low-pass CT ΣΔ ADC with 12-bits resolution in 25MHz bandwidth and low power consumption using 0.18μm CMOS technology. Continuous-time filters are more suitable than discrete-time filters due to relaxed amplifier bandwidth requirements for high frequency ΣΔ ADCs. A fifth-order low-pass filter with cut-off frequency of 25 MHz was designed to meet the dynamic range requirement of the ADC. An active RC topology was chosen for the implementation of the loop filter, which can provide high dynamic range required by the ΣΔ ADC. The design of a summing amplifier and a novel method for adjusting the group delay in the fast path provided by a secondary feedback DAC of the ΣΔ ADC are presented in detail. The ADC was fabricated using Jazz 0.18μm CMOS technology. The implementation issues of OTAs with high-linearity and low-noise performance suitable for the broadband ADC applications are also analyzed in this work. Important design equations pertaining to the linearity and noise performance of the Gm-C biquad filters are presented. A Gm-C biquad with 100MHz center frequency and quality factor 10 was designed as a prototype to confirm with the theoretical design equations. Transistor level circuit implementation of all the analog modules was completed in a standard 0.18μm CMOS process

Diseño de un Modulador ΣΔ en tiempo continuo utilizando el transistor de compuerta flotante

El presente trabajo aborda el diseño y desarrollo de un modulador ΣΔ en tiempo continuo en modo diferencial para la conversión analógica a digital de señales de baja frecuencia. El modulador es diseñado con circuitos que consumen baja potencia y bajo voltaje, utilizando transistores de compuerta flotante (FGMOS); cuya característica principal es que su voltaje de umbral es controlado por N voltajes de entrada acoplados a la compuerta flotante a través de capacitores. El sistema se integra para su realización microelectrónica utilizando diferentes bloques, tales como, integradores Gm-C operando como filtros pasa-bajos, un comparador operando como cuantizador de un bit y, pares diferenciales como convertidores de digital-analógico. Esto, conlleva a contar con técnicas de sobre muestreo con una alta velocidad de procesamiento en tiempo real. Por lo tanto, el diseño y desarrollo toma en cuenta técnicas de procesos CMOS de 0.5 μm, para su realizació

Advanced measurement systems based on digital processing techniques for superconducting LHC magnets

The Large Hadron Collider (LHC), a particle accelerator aimed at exploring deeper into matter than ever before, is currently being constructed at CERN. Beam optics of the LHC, requires stringent control of the field quality of about 8400 superconducting magnets, including 1232 main dipoles and 360 main quadrupoles to assure the correct machine operation. The measurement challenges are various: accuracy on the field strength measurement up to 50 ppm, harmonics in the ppm range, measurement equipment robustness, low measurement times to characterize fast field phenomena. New magnetic measurement systems, principally based on analog solutions, have been developed at CERN to achieve these goals. This work proposes the introduction of digital technologies to improve measurement performance of three systems, aimed at different measurement target and characterized by different accuracy levels. The high accuracy measurement systems, based on rotating coils, exhibit high performance in static magnetic field. With varying magnetic field the system accuracy gets worse, independently from coil speed, due to the limited resolution of the digital integrator currently used, and the restrictions of the standard analysis. A new integrator based on ADC conversion and numerical integration is proposed. The experimental concept validation by emulating the proposed approach on a PXI platform is detailed along with the improvements with respect to the old integrators. Two new analysis algorithms to reduce the errors in dynamic measurements are presented. The first combines quadrature detection and short time Fourier transform (STFT) of the acquired magnetic flux samples; the second approach is based on the extrapolation of the magnetic flux samples. Unlike other algorithms presented in the literature, both the proposals do not require the information about the magnet current and are able to work in real time so, can be easily implemented in firmware on DSP. The performance of the new proposals are assessed in simulation. As far as medium accuracy systems are concerned, at CERN was originally developed a probe to measure the sextupolar and decapolar field harmonics of the superconducting dipoles using a suitable Hall plates arrangement for the bucking of the main dipolar field, which is, 4 orders of magnitude higher than the measurement target. The output signals of each Hall plate belonging to the same measurement ring are mixed using analog cards. The resultant signal is proportional to the field harmonic to measure. A complete metrological characterization of this sensor was carried out, showing the limitation of a fully analog solution. The main problems found were the instability of the analog compensation cards and the impossibility to correct the non linearity effects beyond the first order. An automatic calibration procedure implemented in the new instrument software is presented to guarantee measurement repeatability. In alternative a digital bucking solution, namely the compensation of the main field after the sampling of each hall plate signal by means of numerical sum, is proposed. An implementation of this approach, based on 18 bit ADC converter, over-sampling and dithering techniques as well as compensation of the Hall plates non linearity in real time is analyzed. Finally, as far as the low accuracy measurement systems are concerned, the design of an instrument based on a rotating Hall plate to check the polarity of all LHC magnets is presented. Even if this architecture is characterized by low accuracy in the measurement of field strength and phase, the results are sufficient to identify main harmonic order, type and polarity with practically no errors, thanks to an accurate definition of the measurement algorithm. A complete metrological characterization of the prototype developed and a correction of all the systematic measurement errors was carried out. This instrument, integrated in a test bench developed ad hoc, is become the standard at CERN for the polarity test of all the magnets will compose the machine

Design of adaptive analog filters for magnetic front-end read channels

Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem para canais de leitura em sistemas de gravação e reprodução de dados em suporte magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a 1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços muito significativos a nível mundial com o objectivo de se investigarem novas técnicas de realização de filtros em circuito integrado monolítico, especialmente em tecnologia CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização de soluções com as características desejadas. Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão de sinal bem como a escolha de bons modelos matemáticos para o tratamento da informação e a minimização de erro inerente às aproximações na conformidade aos princípios físicos dos dispositivos caracterizados. O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo, baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization) com base na igualização de sinal utilizando filtros integrados analógicos em tempo contínuo. Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo, dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa e análise de estruturas ideais no projecto de filtros recorrendo a representações no espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de circuitos de transcondutância para a implementação de filtros integrados analógicos em tempo contínuo. Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros no espaço de estados, correspondentes a duas soluções alternativas para a realização de um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem, para utilização num canal de leitura de dados em suporte magnético. Como parte constituinte destes filtros, apresenta-se uma técnica de realização de circuitos de transcondutância, e de realização de condensadores lineares usando matrizes de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se métodos de adaptação automática capazes de compensar os erros face aos valores nominais dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os quais apresentamos os resultados de simulação e de medição experimental obtidos. Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível de constituir uma solução para o controlo de posicionamento da cabeça de leitura em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo de igualação do canal de leitura. Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa utilizado em discos rígidos amovíveis.This thesis studies the design and behavior of continuous-time very-high-frequency filters. The motivation of this work was the search for filtering solutions for the readchannel in recording and reproduction of data on magnetic media systems, with costs and consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than the available circuits. Accordingly, as was done in this work, the rapid development of microelectronics technology raised very significant efforts worldwide in order to investigate new techniques for implementing such filters in monolithic integrated circuit, especially in CMOS technology (Complementary Metal Oxide Semiconductor). We present a comparative study on different hierarchical levels of the project, which led to the realization and characterization of solutions with the desired characteristics. In the first level, this study addresses the conceptual question of recording and transmission of signal and the choice of good mathematical models for the processing of information and minimization of error inherent in the approaches and in accordance with the principles of the characterized physical devices. The main work of this thesis is focused on the hierarchical levels of the architecture of the read channel and the integrated circuit implementation of its main block - the filtering block. At the architecture level of the read channel this work presents a comprehensive study on existing methodologies of adaptation and signal recovery of data on magnetic media. This project appears in the sequence of the proposed solution for a lowcost, low consumption, low voltage, low complexity, using CMOS digital technology for the performance of a DFE (Decision Feedback Equalization) based on the equalization of the signal using integrated analog filters in continuous time. At the project level of implementation of the filtering block and techniques for implementing filters and its building components, it was concluded that the technique based on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate for the implementation of very-high-frequency adaptive filters. We defined in this lower level, two sub-levels of depth study for this thesis, namely: research and analysis of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation of continuous time integrated analog filters. Following this study, we present and compare two filtering structures operating in the space of states, corresponding to two alternatives for achieving a realization of an adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a read-channel for magnetic media devices. As a constituent part of these filters, we present a technique for the realization of transconductance circuits and for the implementation of linear capacitors using arrays of MOSFET transistors for signal processing in very-high-frequency integrated circuits using sub-micrometric CMOS technology. We present methods capable of automatic adjustment and compensation for deviation errors in respect to the nominal values of the components inherent to the tolerances of the fabrication process, for which we present the simulation and experimental measurement results obtained. Also as a result of this study, is the presentation of a circuit that provides a solution for the control of the head positioning on recording/playback systems of data on magnetic media. The proposed block is an adaptive first-order filter, based on the same transconductance circuits and equalization techniques proposed and used in the implementation of the adaptive filter for the equalization of the read channel. This filter was designed and included in an integrated circuit (Jaguar) used to control the positioning of the read-head done for ATMEL company in Colorado Springs, and part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company

Modulador Σ∆ en tiempo continuo con cuantificador de baja resolución

El diseño de sistemas electrónicos presenta una tendencia en la autonomía energética y la reducción de la masa y dimensiones de los dispositivos. Los circuitos electronicos para el procesamiento en la conversión de datos del dominio analógico al digital siguen presentando retos importantes. En el diseño de covertidores, la modulación Sigma-Delta sigue contribuyendo a la reducción de recursos y la resilencia a los factores ambientales y la deriva temporal. Los moduladores Sigma-Delta de tiempo continuo se han convertido en una buena opcion para aplicaciones que requieren un bajo consumo de potencia y una alta velocidad en el procesamiento de la información. Este trabajo se basa en el estudio de moduladores Sigma-Delta de tiempo continuo con cuantificador de un bit mostrando el análisis y modelado. La propuesta resulta la topología un modulador Sigma-Delta TC de tercer orden primeramente modelado en bloques de Simulink y posteriormente descrito con algunos bloques usando lenguaje de Verilog-A, alcanzando un SNR de 81.7 dB y una resolución de 13 bits usando una relación de sobre muestreo de 46. Como elemento innovador, la arquitectura propuesta se ha usado como opción para sustituir en transmisores RF los bloques del mezclador y el convertidor analógico digital (ADC).

Assessment of novel power electronic converters for drives applications

Phd ThesisIn the last twenty years, industrial and academic research has produced over one hundred new converter topologies for drives applications. Regrettably, most of the published work has been directed towards a single topology, giving an overall impression of a large number of unconnected, competing techniques. To provide insight into this wide ranging subject area, an overview of converter topologies is presented. Each topology is classified according to its mode of operation and a family tree is derived encompassing all converter types. Selected converters in each class are analysed, simulated and key operational characteristics identified. Issues associated with the practical implementation of analysed topologies are discussed in detail. Of all AC-AC conversion techniques, it is concluded that softswitching converter topologies offer the most attractive alternative to the standard hard switched converter in the power range up to 100kW because of their high performance to cost ratio. Of the softswitching converters, resonant dc-link topologies are shown to produce the poorest output performance although they offer the cheapest solution. Auxiliary pole commutated inverters, on the other hand, can achieve levels of performance approaching those of the hard switched topology while retaining the benefits of softswitching. It is concluded that the auxiliary commutated resonant pole inverter (ACPI) topology offers the greatest potential for exploitation in spite of its relatively high capital cost. Experimental results are presented for a 20kW hard switched inverter and an equivalent 20kW ACPI. In each case the converter controller is implanted using a digital signal processor. For the ACPI, a new control scheme, which eliminates the need for switch current and voltage sensors, is implemented. Results show that the ACPI produces lower overall losses when compared to its hardswitching counterpart. In addition, device voltage stress, output dv/dt and levels of high frequency output harmonics are all reduced. Finally, it is concluded that modularisation of the active devices, optimisation of semiconductor design and a reduction in the number of additional sensors through the use of novel control methods, such as those presented, will all play a part in the realisation of an economically viable system.Research Committee of the University of Newcastle upon Tyn

The Design and Construction of a Green Laser and Fabry-Perot Cavity System for Jefferson Lab\u27s Hall A Compton Polarimeter

A high finesse Fabry-Perot cavity with a frequency doubled green laser (CW, 532 nm) have been built and installed in Hall A of Jefferson Lab for high precision Compton polarimetry project in spring of 2010. It provides a high intensity circularly polarized photon target for measuring the polarization of electron beam with energies from 1.0 GeV to 11.0 GeV in a nondestructive manner. The IR beam (CW, 1064 nm) from a Ytterbium doped fiber laser amplifier seeded by a Nd:YAG narrow linewidth NPRO laser is frequency doubled in by a single-pass Periodically Poled Lithium Niobate (PPMgLN) crystal. The maximum achieved green power at 5 W IR pump power was 1.74 W with a total conversion efficiency of 34.8%. The frequency locking of this green light to the cavity resonance frequency is achieved by giving a feedback to Nd:YAG crystal via laser piezoelectric (PZT) actuator by Pound-Drever-Hall (PDH) technique. The data shows the maximum amplification gain of our cavity is about 4,000 with a corresponding maximum intra-cavity power of 3.7 kW. The polarization transfer function has been measured in order to determine the intra-cavity laser polarization within the measurement uncertainty of 0.7%. The PREx experiment at JLab, used this system for the first time and achieved 1.0% precision in electron beam polarization measurement at 1.0 GeV

Optimization and analysis of the current control loop of VSCs connected to uncertain grids through LCL filters

Premio Extraordinario de Doctorado 2011This thesis focuses on the design and analysis of the control of voltage source converters connected to the grid through LCL filters. Particularly it is centered on grids presenting uncertainty in their intrinsic dynamic parameters and their influence over the inner control loop of a grid converter: the current control. To that end, the thesis follows a three-fold discussion. Firstly, the thesis studies the grid model, its uncertain parameters and presents a proposal to recursively estimate them. The estimation is based on a recursive least-squares optimization procedure applied to the current and voltage measurements, performed in the point of common coupling, expressed in a synchronous reference frame. The synchronization and the reference frame transformation process is specially designed for the proposed system. The optimization process is complemented with an estimation evaluation block that gives a real-time measure of the estimation quality. The influence of those uncertain parameters over the stability of the current control loop of grid converters is the second topic of this thesis. For the case of linear controllers, the analysis is performed by applying the structured singular value mu theory to a parametric uncertainty model that is described in the document. The proposed method extracts safe grid parameters ranges from a previously defined controller and plant model. Special attention is payed to important practical considerations as pure real uncertainty and sampled-data systems analysis. To test the method performance and illustrate its behavior, this dissertation discusses the robustness of three particular examples: a SISO control approach, a MIMO servo-controller approach and a robust H_inf design. For the case of non-linear controllers, the thesis focuses on hysteresis controllers and presents some practical conclusions. After that analysis, the thesis deals with the complementary problem: the design of a robust controller for grid converters connected through LCL filters to grids whose parameters range between known values. As a prior stage, the thesis presents an LQ servo-controller design procedure that may be complemented with the use of state estimators. The control is faced in a synchronous reference frame and directly controls the grid injected current. Once the framework is settled, the thesis proposes a design technique based on a robust Loop-shaping H_inf design procedure complemented with the nu-gap analysis tool. The final part of this dissertation describes the experimental set-up used for testing the presented proposals. After this, a summary of experimental results and waveforms is presented

High performance continuous-time filters for information transfer systems

Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications