112 research outputs found
On Dyadic Parity Check Codes and Their Generalizations
In order to communicate information over a noisy channel, error-correcting codes can be used to ensure that small errors don’t prevent the transmission of a message. One family of codes that has been found to have good properties is low-density parity check (LDPC) codes. These are represented by sparse bipartite graphs and have low complexity graph-based decoding algorithms. Various graphical properties, such as the girth and stopping sets, influence when these algorithms might fail. Additionally, codes based on algebraically structured parity check matrices are desirable in applications due to their compact representations, practical implementation advantages, and tractable decoder performance analysis.
This dissertation focuses on codes based on parity check matrices that are dyadic, n-adic, or quasi-dyadic (QD), meaning the parity check matrix representation is block structured with dyadic matrices as blocks. Depending on the number of nonzero positions in the leading row of each block, these codes may be either low density or moderate density. Since each block is reproducible, the resulting QD codes have similar advantages to quasi-cyclic (QC) codes. We examine basic code properties of dyadic, n-adic, and QD parity check codes, including bounds on the dimension and minimum distance, cycle structure of the corresponding Tanner graph, and their possible use in quantum code constructions. We also consider the relationship between cycle codes of graphs and cycle codes of their lifts.
Advisor: Christine A. Kelle
Bias-tailored quantum LDPC codes
Bias-tailoring allows quantum error correction codes to exploit qubit noise
asymmetry. Recently, it was shown that a modified form of the surface code, the
XZZX code, exhibits considerably improved performance under biased noise. In
this work, we demonstrate that quantum low density parity check codes can be
similarly bias-tailored. We introduce a bias-tailored lifted product code
construction that provides the framework to expand bias-tailoring methods
beyond the family of 2D topological codes. We present examples of bias-tailored
lifted product codes based on classical quasi-cyclic codes and numerically
assess their performance using a belief propagation plus ordered statistics
decoder. Our Monte Carlo simulations, performed under asymmetric noise, show
that bias-tailored codes achieve several orders of magnitude improvement in
their error suppression relative to depolarising noise.Comment: 21 Pages, 13 Figures. Comments welcome
SIGNAL PROCESSING TECHNIQUES AND APPLICATIONS
As the technologies scaling down, more transistors can be fabricated into the same area, which enables the integration of many components into the same substrate, referred to as system-on-chip (SoC). The components on SoC are connected by on-chip global interconnects. It has been shown in the recent International Technology Roadmap of Semiconductors (ITRS) that when scaling down, gate delay decreases, but global interconnect delay increases due to crosstalk. The interconnect delay has become a bottleneck of the overall system performance. Many techniques have been proposed to address crosstalk, such as shielding, buffer insertion, and crosstalk avoidance codes (CACs). The CAC is a promising technique due to its good crosstalk reduction, less power consumption and lower area. In this dissertation, I will present analytical delay models for on-chip interconnects with improved accuracy. This enables us to have a more accurate control of delays for transition patterns and lead to a more efficient CAC, whose worst-case delay is 30-40% smaller than the best of previously proposed CACs. As the clock frequency approaches multi-gigahertz, the parasitic inductance of on-chip interconnects has become significant and its detrimental effects, including increased delay, voltage overshoots and undershoots, and increased crosstalk noise, cannot be ignored. We introduce new CACs to address both capacitive and inductive couplings simultaneously.Quantum computers are more powerful in solving some NP problems than the classical computers. However, quantum computers suffer greatly from unwanted interactions with environment. Quantum error correction codes (QECCs) are needed to protect quantum information against noise and decoherence. Given their good error-correcting performance, it is desirable to adapt existing iterative decoding algorithms of LDPC codes to obtain LDPC-based QECCs. Several QECCs based on nonbinary LDPC codes have been proposed with a much better error-correcting performance than existing quantum codes over a qubit channel. In this dissertation, I will present stabilizer codes based on nonbinary QC-LDPC codes for qubit channels. The results will confirm the observation that QECCs based on nonbinary LDPC codes appear to achieve better performance than QECCs based on binary LDPC codes.As the technologies scaling down further to nanoscale, CMOS devices suffer greatly from the quantum mechanical effects. Some emerging nano devices, such as resonant tunneling diodes (RTDs), quantum cellular automata (QCA), and single electron transistors (SETs), have no such issues and are promising candidates to replace the traditional CMOS devices. Threshold gate, which can implement complex Boolean functions within a single gate, can be easily realized with these devices. Several applications dealing with real-valued signals have already been realized using nanotechnology based threshold gates. Unfortunately, the applications using finite fields, such as error correcting coding and cryptography, have not been realized using nanotechnology. The main obstacle is that they require a great number of exclusive-ORs (XORs), which cannot be realized in a single threshold gate. Besides, the fan-in of a threshold gate in RTD nanotechnology needs to be bounded for both reliability and performance purpose. In this dissertation, I will present a majority-class threshold architecture of XORs with bounded fan-in, and compare it with a Boolean-class architecture. I will show an application of the proposed XORs for the finite field multiplications. The analysis results will show that the majority class outperforms the Boolean class architectures in terms of hardware complexity and latency. I will also introduce a sort-and-search algorithm, which can be used for implementations of any symmetric functions. Since XOR is a special symmetric function, it can be implemented via the sort-and-search algorithm. To leverage the power of multi-input threshold functions, I generalize the previously proposed sort-and-search algorithm from a fan-in of two to arbitrary fan-ins, and propose an architecture of multi-input XORs with bounded fan-ins
Non-Clifford and parallelizable fault-tolerant logical gates on constant and almost-constant rate homological quantum LDPC codes via higher symmetries
We study parallel fault-tolerant quantum computing for families of
homological quantum low-density parity-check (LDPC) codes defined on
3-manifolds with constant or almost-constant encoding rate. We derive generic
formula for a transversal gate of color codes on general 3-manifolds, which
acts as collective non-Clifford logical CCZ gates on any triplet of logical
qubits with their logical- membranes having a triple
intersection at a single point. The triple intersection number is a topological
invariant, which also arises in the path integral of the emergent higher
symmetry operator in a topological quantum field theory: the
gauge theory. Moreover, the transversal gate of the color code corresponds
to a higher-form symmetry supported on a codimension-1 submanifold, giving rise
to exponentially many addressable and parallelizable logical CZ gates. We have
developed a generic formalism to compute the triple intersection invariants for
3-manifolds and also study the scaling of the Betti number and systoles with
volume for various 3-manifolds, which translates to the encoding rate and
distance. We further develop three types of LDPC codes supporting such logical
gates: (1) A quasi-hyperbolic code from the product of 2D hyperbolic surface
and a circle, with almost-constant rate and
distance; (2) A homological fibre bundle code with
rate and distance; (3) A specific family of 3D
hyperbolic codes: the Torelli mapping torus code, constructed from mapping tori
of a pseudo-Anosov element in the Torelli subgroup, which has constant rate
while the distance scaling is currently unknown. We then show a generic
constant-overhead scheme for applying a parallelizable universal gate set with
the aid of logical- measurements.Comment: 40 pages, 31 figure
On generalized LDPC codes for ultra reliable communication
Ultra reliable low latency communication (URLLC) is an important feature in
future mobile communication systems, as they will require high data rates, large
system capacity and massive device connectivity [11]. To meet such stringent
requirements, many error-correction codes (ECC)s are being investigated; turbo
codes, low density parity check (LDPC) codes, polar codes and convolutional codes
[70, 92, 38], among many others. In this work, we present generalized low density
parity check (GLDPC) codes as a promising candidate for URLLC.
Our proposal is based on a novel class of GLDPC code ensembles, for which
new analysis tools are proposed. We analyze the trade-o_ between coding rate and
asymptotic performance of a class of GLDPC codes constructed by including a
certain fraction of generalized constraint (GC) nodes in the graph. To incorporate
both bounded distance (BD) and maximum likelihood (ML) decoding at GC nodes
into our analysis without resorting to multi-edge type of degree distribution (DD)s,
we propose the probabilistic peeling decoding (P-PD) algorithm, which models the
decoding step at every GC node as an instance of a Bernoulli random variable with
a successful decoding probability that depends on both the GC block code as well
as its decoding algorithm. The P-PD asymptotic performance over the BEC can
be efficiently predicted using standard techniques for LDPC codes such as Density
evolution (DE) or the differential equation method. We demonstrate that the
simulated P-PD performance accurately predicts the actual performance of the
GLPDC code under ML decoding at GC nodes. We illustrate our analysis for
GLDPC code ensembles with regular and irregular DDs.
This design methodology is applied to construct practical codes for URLLC.
To this end, we incorporate to our analysis the use of quasi-cyclic (QC) structures,
to mitigate the code error floor and facilitate the code very large scale integration
(VLSI) implementation. Furthermore, for the additive white Gaussian noise
(AWGN) channel, we analyze the complexity and performance of the message
passing decoder with various update rules (including standard full-precision sum product and min-sum algorithms) and quantization schemes. The block error rate
(BLER) performance of the proposed GLDPC codes, combined with a complementary
outer code, is shown to outperform a variety of state-of-the-art codes, for
URLLC, including LDPC codes, polar codes, turbo codes and convolutional codes,
at similar complexity rates.Programa Oficial de Doctorado en Multimedia y ComunicacionesPresidente: Juan José Murillo Fuentes.- Secretario: Matilde Pilar Sánchez Fernández.- Vocal: Javier Valls Coquilla
Balanced Product Quantum Codes
This work provides the first explicit and non-random family of
LDPC quantum codes which encode logical qubits
with distance . The family is constructed by
amalgamating classical codes and Ramanujan graphs via an operation called
balanced product.
Recently, Hastings-Haah-O'Donnell and Panteleev-Kalachev were the first to
show that there exist families of LDPC quantum codes which break the
distance barrier. However, their
constructions are based on probabilistic arguments which only guarantee the
code parameters with high probability whereas our bounds hold unconditionally.
Further, balanced products allow for non-abelian twisting of the check
matrices, leading to a construction of LDPC quantum codes that can be shown to
have and that we conjecture to have linear distance .Comment: 23 pages, 11 figure
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