Testability considerations for implementing an embedded memory subsystem

textThere are a number of testability considerations for VLSI design, but test coverage, test time, accuracy of test patterns and correctness of design information for DFD (Design for debug) are the most important ones in design with embedded memories. The goal of DFT (Design-for-Test) is to achieve zero defects. When it comes to the memory subsystem in SOCs (system on chips), many flavors of memory BIST (built-in self test) are able to get high test coverage in a memory, but often, no proper attention is given to the memory interface logic (shadow logic). Functional testing and BIST are the most prevalent tests for this logic, but functional testing is impractical for complicated SOC designs. As a result, industry has widely used at-speed scan testing to detect delay induced defects. Compared with functional testing, scan-based testing for delay faults reduces overall pattern generation complexity and cost by enhancing both controllability and observability of flip-flops. However, without proper modeling of memory, Xs are generated from memories. Also, when the design has chip compression logic, the number of ATPG patterns is increased significantly due to Xs from memories. In this dissertation, a register based testing method and X prevention logic are presented to tackle these problems. An important design stage for scan based testing with memory subsystems is the step to create a gate level model and verify with this model. The flow needs to provide a robust ATPG netlist model. Most industry standard CAD tools used to analyze fault coverage and generate test vectors require gate level models. However, custom embedded memories are typically designed using a transistor-level flow, there is a need for an abstraction step to generate the gate models, which must be equivalent to the actual design (transistor level). The contribution of the research is a framework to verify that the gate level representation of custom designs is equivalent to the transistor-level design. Compared to basic stuck-at fault testing, the number of patterns for at-speed testing is much larger than for basic stuck-at fault testing. So reducing test and data volume are important. In this desertion, a new scan reordering method is introduced to reduce test data with an optimal routing solution. With in depth understanding of embedded memories and flows developed during the study of custom memory DFT, a custom embedded memory Bit Mapping method using a symbolic simulator is presented in the last chapter to achieve high yield for memories.Electrical and Computer Engineerin

LOW POWER AND LOW AREA MULTIPLICATION CIRCUITS THROUGH PARTIAL PRODUCT PERFORATION

Focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. The partial product perforation method for creating approximate multipliers. It omit the generation of some partial products, thus reducing the number of partial products that have to be accumulated; we decrease the area, power. The major contributions of this work, the software-based perforation technique on the design of hardware circuits, obtaining the optimized design solutions regarding the power–area–error tradeoffs. Analyze in a mathematically rigorous manner the arithmetic accuracy of partial product perforation and prove that it delivers a bounded and predictable output error. Error analysis is not bound to specific multiplier architecture and can be applied with error guarantees to every multiplication circuit regardless of its architecture that compared with the respective exact design, the partial product perforation. Index Terms: Approximate Arithmetic Circuits, Approximate Computing, Approximate Multiplier, Error Analysis & Low Power

Lempel Ziv Welch data compression using associative processing as an enabling technology for real time application

Data compression is a term that refers to the reduction of data representation requirements either in storage and/or in transmission. A commonly used algorithm for compression is the Lempel-Ziv-Welch (LZW) method proposed by Terry A. Welch[l]. LZW is an adaptive, dictionary based, lossless algorithm. This provides for a general compression mechanism that is applicable to a broad range of inputs. Furthermore, the lossless nature of LZW implies that it is a reversible process which results in the original file/message being fully recoverable from compression. A variant of this algorithm is currently the foundation of the UNIX compress program. Additionally, LZW is one of the compression schemes defined in the TIFF standard[12], as well as in the CCITT V.42bis standard. One of the challenges in designing an efficient compression mechanism, such as LZW, which can be used in real time applications, is the speed of the search into the data dictionary. In this paper an Associative Processing implementation of the LZW algorithm is presented. This approach provides an efficient solution to this requirement. Additionally, it is shown that Associative Processing (ASP) allows for rapid and elegant development of the LZW algorithm that will generally outperform standard approaches in complexity, readability, and performance

Commissioning the ATLAS Silicon Microstrip Tracker

The completed SemiConductor Tracker (SCT) has been installed inside ATLAS. Tests were performed last year to verify the connectivity of the electrical and optical services. Problems observed with the heaters for the evaporative cooling system have been resolved. This has enabled extended operation of the full detector under realistic conditions. Calibration data has been taken and analyzed to determine the noise performance of the system. In addition, extensive commissioning with cosmic ray events has started. The cosmic muon data has been used to align the detector, to check the timing of the front-end electronics as well as to check hit efficiency of modules. The current status of the SCT will be reviewed

Automated Debugging Methodology for FPGA-based Systems

Electronic devices make up a vital part of our lives. These are seen from mobiles, laptops, computers, home automation, etc. to name a few. The modern designs constitute billions of transistors. However, with this evolution, ensuring that the devices fulfill the designer’s expectation under variable conditions has also become a great challenge. This requires a lot of design time and effort. Whenever an error is encountered, the process is re-started. Hence, it is desired to minimize the number of spins required to achieve an error-free product, as each spin results in loss of time and effort. Software-based simulation systems present the main technique to ensure the verification of the design before fabrication. However, few design errors (bugs) are likely to escape the simulation process. Such bugs subsequently appear during the post-silicon phase. Finding such bugs is time-consuming due to inherent invisibility of the hardware. Instead of software simulation of the design in the pre-silicon phase, post-silicon techniques permit the designers to verify the functionality through the physical implementations of the design. The main benefit of the methodology is that the implemented design in the post-silicon phase runs many order-of-magnitude faster than its counterpart in pre-silicon. This allows the designers to validate their design more exhaustively. This thesis presents five main contributions to enable a fast and automated debugging solution for reconfigurable hardware. During the research work, we used an obstacle avoidance system for robotic vehicles as a use case to illustrate how to apply the proposed debugging solution in practical environments. The first contribution presents a debugging system capable of providing a lossless trace of debugging data which permits a cycle-accurate replay. This methodology ensures capturing permanent as well as intermittent errors in the implemented design. The contribution also describes a solution to enhance hardware observability. It is proposed to utilize processor-configurable concentration networks, employ debug data compression to transmit the data more efficiently, and partially reconfiguring the debugging system at run-time to save the time required for design re-compilation as well as preserve the timing closure. The second contribution presents a solution for communication-centric designs. Furthermore, solutions for designs with multi-clock domains are also discussed. The third contribution presents a priority-based signal selection methodology to identify the signals which can be more helpful during the debugging process. A connectivity generation tool is also presented which can map the identified signals to the debugging system. The fourth contribution presents an automated error detection solution which can help in capturing the permanent as well as intermittent errors without continuous monitoring of debugging data. The proposed solution works for designs even in the absence of golden reference. The fifth contribution proposes to use artificial intelligence for post-silicon debugging. We presented a novel idea of using a recurrent neural network for debugging when a golden reference is present for training the network. Furthermore, the idea was also extended to designs where golden reference is not present

The CUORE cryostat: an infrastructure for rare event searches at millikelvin temperatures

The CUORE experiment is the world's largest bolometric experiment. The detector consists of an array of 988 TeO2 crystals, for a total mass of 742 kg. CUORE is presently taking data at the Laboratori Nazionali del Gran Sasso, Italy, searching for the neutrinoless double beta decay of 130Te. A large custom cryogen-free cryostat allows reaching and maintaining a base temperature of about 10 mK, required for the optimal operation of the detector. This apparatus has been designed in order to achieve a low noise environment, with minimal contribution to the radioactive background for the experiment. In this paper, we present an overview of the CUORE cryostat, together with a description of all its sub-systems, focusing on the solutions identified to satisfy the stringent requirements. We briefly illustrate the various phases of the cryostat commissioning and highlight the relevant steps and milestones achieved each time. Finally, we describe the successful cooldown of CUORE

Diseño, implementación y optimización del sistema de compresión de imágenes sobre el ordenador de a bordo del proyecto de nanosátelite Eye-Sat

Eye-Sat es un Proyecto de nano satélites, dirigido por el CNES (Centre National d’Etudes Spatiales) y desarrollado principalmente por estudiantes de varias escuelas de ingeniería del territorio francés. El objetivo de este pequeño telescopio no solo radica en la oportunidad de realizar la demostración de distintos dispositivos tecnológicos, sino que también tiene como misión la adquisición de fotografías en la bandas de color e infrarrojo de la vía Láctea, así como el estudio de la intensidad y polarización de la luz Zodiacal. Los requerimientos de la misión exigen el desarrollo de un algoritmo de compresión de imágenes sin pérdidas para las imágenes “Color Filter Array” CFA (Bayer) e infrarrojas adquiridas por el satélite. Como miembro de la comisión consultativa para los sistemas espaciales, CNES ha seleccionado el estándar CCSDS-123.0-B como algoritmo base para cumplir los requerimientos de la misión. A este algoritmo se le añadirán modificaciones o mejoras, adaptadas a las imágenes tipo, con el fin de mejorar las prestaciones de compresión y de complejidad. La implementación y la optimización del algoritmo será desarrollada sobre la plataforma Xilinx Zynq® All Programmable SoC, el cual incluye una FPGA y un Dual-core ARM® Cortex™-A9 processor with NEONTM DSP/FPU Engine

Automotive Stirling Engine Development Program

Activities performed on Mod I engine testing and test results; the manufacture, assembly, and test of a Mod I engine in the United States; design initiation of the Mod I-A engine system; transient performance testing; Stirling reference engine manufacturing and reduced size studies; components and subsystems; and the study and test of low cost alloys are summarized

Design and development of auxiliary components for a new two-stroke, stratified-charge, lean-burn gasoline engine

A unique stepped-piston engine was developed by a group of research engineers at Universiti Teknologi Malaysia (UTM), from 2003 to 2005. The development work undertaken by them engulfs design, prototyping and evaluation over a predetermined period of time which was iterative and challenging in nature. The main objective of the program is to demonstrate local R&D capabilities on small engine work that is able to produce mobile powerhouse of comparable output, having low-fuel consumption and acceptable emission than its crankcase counterpart of similar displacement. A two-stroke engine work was selected as it posses a number of technological challenges, increase in its thermal efficiency, which upon successful undertakings will be useful in assisting the group in future powertrain undertakings in UTM. In its carbureted version, the single-cylinder aircooled engine incorporates a three-port transfer system and a dedicated crankcase breather. These features will enable the prototype to have high induction efficiency and to behave very much a two-stroke engine but equipped with a four-stroke crankcase lubrication system. After a series of analytical work the engine was subjected to a series of laboratory trials. It was also tested on a small watercraft platform with promising indication of its flexibility of use as a prime mover in mobile platform. In an effort to further enhance its technology features, the researchers have also embarked on the development of an add-on auxiliary system. The system comprises of an engine control unit (ECU), a directinjector unit, a dedicated lubricant dispenser unit and an embedded common rail fuel unit. This support system was incorporated onto the engine to demonstrate the finer points of environmental-friendly and fuel economy features. The outcome of this complete package is described in the report, covering the methodology and the final characteristics of the mobile power plant