21 research outputs found
CROSS-LAYER DESIGN, OPTIMIZATION AND PROTOTYPING OF NoCs FOR THE NEXT GENERATION OF HOMOGENEOUS MANY-CORE SYSTEMS
This thesis provides a whole set of design methods to enable and manage the
runtime heterogeneity of features-rich industry-ready Tile-Based Networkon-
Chips at different abstraction layers (Architecture Design, Network Assembling,
Testing of NoC, Runtime Operation). The key idea is to maintain
the functionalities of the original layers, and to improve the performance
of architectures by allowing, joint optimization and layer coordinations. In
general purpose systems, we address the microarchitectural challenges by codesigning
and co-optimizing feature-rich architectures. In application-specific
NoCs, we emphasize the event notification, so that the platform is continuously
under control. At the network assembly level, this thesis proposes a
Hold Time Robustness technique, to tackle the hold time issue in synchronous
NoCs. At the network architectural level, the choice of a suitable synchronization
paradigm requires a boost of synthesis flow as well as the coexistence
with the DVFS. On one hand this implies the coexistence of mesochronous
synchronizers in the network with dual-clock FIFOs at network boundaries.
On the other hand, dual-clock FIFOs may be placed across inter-switch links
hence removing the need for mesochronous synchronizers. This thesis will
study the implications of the above approaches both on the design flow and
on the performance and power quality metrics of the network. Once the manycore
system is composed together, the issue of testing it arises. This thesis
takes on this challenge and engineers various testing infrastructures. At the
upper abstraction layer, the thesis addresses the issue of managing the fully
operational system and proposes a congestion management technique named
HACS. Moreover, some of the ideas of this thesis will undergo an FPGA
prototyping. Finally, we provide some features for emerging technology by
characterizing the power consumption of Optical NoC Interfaces
An efficient asynchronous spatial division multiplexing router for network-on-chip on the hardware platform
The quasi-delay-insensitive (QDI) based asynchronous network-on-chip (ANoC) has several advantages over clock-based synchronous network-on-chips (NoCs). The asynchronous router uses a virtual channel (VC) as a primary flow-control mechanism however, the spatial division multiplexing (SDM) based mechanism performs better over input traffics over VC. This manuscript uses an asynchronous spatial division multiplexing (ASDM) based router for NoC architecture on a field-programmable gate array (FPGA) platform. The ASDM router is configurable to different bandwidths and VCs. The ASDM router mainly contains input-output (I/O) buffers, a switching allocator, and a crossbar unit. The 4-phase 1-of-4 dual-rail protocol is used to construct the I/O buffers. The performance of the ASDM router is analyzed in terms of lower urinary tract symptoms (LUTs) (chip area), delay, latency, and throughput parameters. The work is implemented using Verilog-HDL with Xilinx ISE 14.7 on artix-7 FPGA. The ASDM router achieves % chip area and obtains 0.8 ns of latency with a throughput of 800 Mfps. The proposed router is compared with existing asynchronous approaches with improved latency and throughput metrics
Design and Validation of Network-on-Chip Architectures for the Next Generation of Multi-synchronous, Reliable, and Reconfigurable Embedded Systems
NETWORK-ON-CHIP (NoC) design is today at a crossroad. On one hand, the
design principles to efficiently implement interconnection networks in the
resource-constrained on-chip setting have stabilized. On the other hand,
the requirements on embedded system design are far from stabilizing. Embedded
systems are composed by assembling together heterogeneous components featuring
differentiated operating speeds and ad-hoc counter measures must be adopted
to bridge frequency domains. Moreover, an unmistakable trend toward enhanced
reconfigurability is clearly underway due to the increasing complexity of applications.
At the same time, the technology effect is manyfold since it provides unprecedented
levels of system integration but it also brings new severe constraints
to the forefront: power budget restrictions, overheating concerns, circuit delay and
power variability, permanent fault, increased probability of transient faults.
Supporting different degrees of reconfigurability and flexibility in the parallel
hardware platform cannot be however achieved with the incremental evolution of
current design techniques, but requires a disruptive approach and a major increase
in complexity. In addition, new reliability challenges cannot be solved by using
traditional fault tolerance techniques alone but the reliability approach must be
also part of the overall reconfiguration methodology.
In this thesis we take on the challenge of engineering a NoC architectures for
the next generation systems and we provide design methods able to overcome the
conventional way of implementing multi-synchronous, reliable and reconfigurable
NoC. Our analysis is not only limited to research novel approaches to the specific
challenges of the NoC architecture but we also co-design the solutions in a single
integrated framework. Interdependencies between different NoC features are
detected ahead of time and we finally avoid the engineering of highly optimized solutions
to specific problems that however coexist inefficiently together in the final
NoC architecture. To conclude, a silicon implementation by means of a testchip
tape-out and a prototype on a FPGA board validate the feasibility and effectivenes
Addressing Manufacturing Challenges in NoC-based ULSI Designs
Hernández Luz, C. (2012). Addressing Manufacturing Challenges in NoC-based ULSI Designs [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1669
Asynchronous interfaces for IOPT-Flow to support GALS systems
45th Annual Conference of the IEEE Industrial Electronics Society: Lisbon, Portugal: oct. 14-17, 2019Throughout the course of time, distributing a global clock signal over a synchronous circuit has become a demanding task as a result of the broadening size and complexity of modern circuits. Globally Asynchronous Locally Synchronous (GALS) systems emerge as a solution to the laborious task of distributing a global clock over a large circuit, through the partitioning of said circuit into smaller, and therefore, more manageable blocks. The DS-Pnet (Dataflow, Signals and Petri nets) modelling language and its associated framework IOPT-Flow focus on supporting the development of cyber-physical systems, however, they may be a strong push to the development of GALS systems, through their multiple available tools that comprise a graphical editor, a simulator and automatic code generation tools, namely a VHDL (VHSIC Hardware Description Language) code generator. In order to facilitate the implementation of said GALS system in the IOPT-Flow framework, some components were created, these work together to form asynchronous interfaces that are a crucial element to any GALS system, thus providing options to designers that intent to develop a GALS system utilizing the IOPT-Flow framework
On-Chip-Netzwerk-Architekturen für eingebettete hierarchische Multiprozessoren
Ax J. On-Chip-Netzwerk-Architekturen für eingebettete hierarchische Multiprozessoren. Bielefeld: Universität Bielefeld; 2019.Das Ziel der vorliegenden Arbeit ist die Realisierung und Analyse einer skalierbaren
Verbindungsstruktur für ein Multi-Prozessorsystem auf einem Chip (MPSoC). Durch
die zunehmende Digitalisierung werden in immer mehr Geräten des täglichen Lebens
und der Industrie mikroelektronische Systeme eingesetzt. Hierbei handelt es sich häufig
um energiebeschränkte Systeme, die zusätzlich einen stetig steigenden Bedarf an
Rechenleistung aufweisen. Ein Trend, diesen Bedarf zu decken ist die Integration von
zunehmend mehr Prozessorkernen auf einem einzelnen Mikrochip. Many-Core-Systeme
mit vielen hunderten bis tausenden ressourceneffizienten CPU-Kernen versprechen
hierbei eine besonders hohe Energieeffizienz. Im Vergleich zu Systemen mit wenigen
leistungsfähigen, jedoch auch komplexeren CPUs, wird bei Many-Cores die Rechenleistung
durch massive Parallelität erzielt. In der AG Kognitronik und Sensorik der
Universität Bielefeld wird dazu das CoreVA-MPSoC entwickelt. Um hunderte von CPUs
auf einen Chip zu integrieren, verfügt das CoreVA-MPSoC über eine hierarchische
Verbindungsstruktur. Diese besteht aus einem On-Chip-Netzwerk (NoC), welches eine
Vielzahl von CPU-Cluster koppelt. In jedem CPU-Cluster sind mehrere ressourceneffiziente
VLIW-Prozessorkerne über eine eng gekoppelte Bus-Struktur verbunden.
Der Fokus dieser Arbeit ist die Entwicklung und Entwurfsraumexploration einer
ressourceneffizienten NoC-Architektur für den Einsatz im CoreVA-MPSoC. Die Entwurfsraumexploration
findet dazu auf verschiedenen Ebenen statt. Auf der Ebene der
Verbindungsstruktur des NoCs werden verschiedene Topologien und Mechanismen der
Flusskontrolle untersucht. Des Weiteren wird die Entwicklung und Analyse eines synchronen,
mesochronen und asynchronen NoCs vorgestellt, um die Skalierbarkeit und
Energieeffizienz dieser Methoden zu untersuchen. Eine weitere Ebene bildet die Schnittstelle
zum Prozessorsystem bzw. CPU-Cluster, die einen maßgeblichen Einfluss auf die
Softwareentwicklung und Gesamtperformanz des Systems hat. Auf Systemebene wird
schließlich die Anbindung verschiedener Speicherarchitekturen an das NoC vorgestellt
und deren Auswirkung auf Performanz und Energiebedarf analysiert. Ein abstraktes
Modell des CoreVA-MPSoCs mit Fokus auf dem NoC erlaubt die Abschätzung von Fläche,
Performanz und Energie des Systems, bzw. der Ausführung von Streaming-Anwendungen.
Dieses Modell kann im CoreVA-MPSoC-Compiler für die automatische Abbildung
von Anwendungen auf dem MPSoC eingesetzt werden. Zehn Streaming-Anwendungen,
vorwiegend aus dem Bereich der Signal- und Bildverarbeitung, zeigen bei der Abbildung
auf einem CoreVA-MPSoC mit 32 CPUs eine durchschnittliche Beschleunigung um den
Faktor 24 gegenüber der Ausführung auf einer CPU.
Ein CoreVA-MPSoC mit 64 CPUs und insgesamt 3MB Speicher besitzt bei einer prototypischen
Implementierung in einer 28-nm-FD-SOI-Standardzellenbibliothek einen
Flächenbedarf von 14,4mm2. Bei einer Taktfrequenz von 700MHz liegt die durchschnittliche
Leistungsaufnahme bei 2W. Eine FPGA-basierte Emulation auf einem
FPGA-Cluster aus Xilinx Virtex-5-FPGAs erlaubt zudem eine skalierbare Verifikation
eines CoreVA-MPSoCs mit nahezu beliebig vielen CPUs
CoreVA-MPSoC: A Many-core Architecture with Tightly Coupled Shared and Local Data Memories
Ax J, Sievers G, Daberkow J, et al. CoreVA-MPSoC: A Many-core Architecture with Tightly Coupled Shared and Local Data Memories. IEEE Transactions on Parallel and Distributed Systems. 2018;29(5):1030-1043
Developing Globally-Asynchronous Locally- Synchronous Systems through the IOPT-Flow Framework
Throughout the years, synchronous circuits have increased in size and com-plexity, consequently, distributing a global clock signal has become a laborious task. Globally-Asynchronous Locally-Synchronous (GALS) systems emerge as a possible solution; however, these new systems require new tools.
The DS-Pnet language formalism and the IOPT-Flow framework aim to support and accelerate the development of cyber-physical systems. To do so it offers a tool chain that comprises a graphical editor, a simulator and code gener-ation tools capable of generating C, JavaScript and VHDL code. However, DS-Pnets and IOPT-Flow are not yet tuned to handle GALS systems, allowing for partial specification, but not a complete one.
This dissertation proposes extensions to the DS-Pnet language and the IOPT-Flow framework in order to allow development of GALS systems. Addi-tionally, some asynchronous components were created, these form interfaces that allow synchronous blocks within a GALS system to communicate with each other
Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design
This dissertation presents three design solutions to support several key system-on-chip (SoC) issues to achieve low-power and high performance. These are: 1) joint source and channel decoding (JSCD) schemes for low-power SoCs used in portable multimedia systems, 2) efficient on-chip interconnect architecture for massive multimedia data streaming on multiprocessor SoCs (MPSoCs), and 3) data processing architecture for low-power SoCs in distributed sensor network (DSS) systems and its implementation.
The first part includes a low-power embedded low density parity check code (LDPC) - H.264 joint decoding architecture to lower the baseband energy consumption of a channel decoder using joint source decoding and dynamic voltage and frequency scaling (DVFS). A low-power multiple-input multiple-output (MIMO) and H.264 video joint detector/decoder design that minimizes energy for portable, wireless embedded systems is also designed.
In the second part, a link-level quality of service (QoS) scheme using unequal error protection (UEP) for low-power network-on-chip (NoC) and low latency on-chip network designs for MPSoCs is proposed. This part contains WaveSync, a low-latency focused network-on-chip architecture for globally-asynchronous locally-synchronous (GALS) designs and a simultaneous dual-path routing (SDPR) scheme utilizing path diversity present in typical mesh topology network-on-chips. SDPR is akin to having a higher link width but without the significant hardware overhead associated with simple bus width scaling.
The last part shows data processing unit designs for embedded SoCs. We propose a data processing and control logic design for a new radiation detection sensor system generating data at or above Peta-bits-per-second level. Implementation results show that the intended clock rate is achieved within the power target of less than 200mW. We also present a digital signal processing (DSP) accelerator supporting configurable MAC, FFT, FIR, and 3-D cross product operations for embedded SoCs. It consumes 12.35mW along with 0.167mm2 area at 333MHz