Switchless compact dual-band matching networks for class-E power amplifiers

Two compact switchless dual-band load networks for class-E power amplifier (PA) operating at 800 and 1900 MHz are proposed, featuring small area and low loss which will be suitable for non-concurrent dual-band PA module in handset. Theoretical analysis and design equations are provided along with a loss model, including loss in the transistor and in the load network. Loss model is extracted for each structure to find the design parameters for optimized and balanced efficiency in both bands. Both designs are fabricated on Rogers RO4003 substrate with lumped components. Full PA simulations of both bands are carried out with co-simulation using a Triquint TGF2023-2-10 GaN transistor model, lumped components and EM models of load network layouts for both structures. The PA with transformer-based load network achieves a power added efficiency of 68.6 % at low band and 62.6 % at high band at an output power of 37.8 and 36.7 dBm respectively. The overall area consumed by the load network is 13.5 × 9.6 mm2. The LC-based PA has a similar PAE of 68.3 and 60 % at low band and high band, respectively. The output power is 38.1 dBm in the low band and 37 dBm in the high-band. The overall area consumed by the load network is 9 × 10 mm

Millimeter-Wave Concurrent Dual-Band Sige Bicmos Rfic Phased-Array Transmitter and Components

A concurrent dual-band phased-array transmitter (TX) and its constituent components are studied in this dissertation. The TX and components are designed for the unlicensed bands, 22–29 and 57–64 GHz, using a 0.18-μm BiCMOS technology. Various studies have been done to design the components, which are suitable for the concurrent dual-band phased-array TX. The designed and developed components in this study are an attenuator, switch, phase shifter, power amplifier and power divider. Attenuators play a key role in tailoring main beam and side-lobe patterns in a phased-array TX. To perform the function in the concurrent dual-band phased-array TX, a 22–29 and 57–64 GHz concurrent dual-band attenuator with low phase variations is designed. Signal detection paths are employed at the output of the phased-array TX to monitor the phase and amplitude deviations/errors, which are larger in the high-frequency design. The detected information enables the TX to have an accurate beam tailoring and steering. A 10–67 GHz wide-band attenuator, covering the dual bands, is designed to manipulate the amplitude of the detected signal. New design techniques for an attenuator with a wide attenuation range and improved flatness are proposed. Also, a topology of dual-function circuit, attenuation and switching, is proposed. The switching turns on and off the detection path to minimize the leakages while the path is not used. Switches are used to minimize the number of components in the phased-array transceiver. With the switches, some of the bi-directional components in the transceiver such as an attenuator, phase shifter, filter, and antenna can be shared by the TX and receiver (RX) parts. In this dissertation, a high-isolation switch with a band-pass filtering response is proposed. The band-pass filtering response suppresses the undesired harmonics and intermodulation products of the TX. Phase shifters are used in phased-array TXs to steer the direction of the beam. A 24-GHz phase shifter with low insertion loss variation is designed using a transistor-body-floating technique for our phased-array TX. The low insertion loss variation minimizes the interference in the amplitude control operation (by attenuator or variable gain amplifier) in phased-array systems. BJTs in a BiCMOS process are characterized across dc to 67 GHz. A novel characterization technique, using on-wafer calibration and EM-based de-embedding both, is proposed and its accuracy at high frequencies is verified. The characterized BJT is used in designing the amplifiers in the phased-array TX. A concurrent dual-band power amplifier (PA) centered at 24 and 60 GHz is proposed and designed for the dual-band phased-array TX. Since the PA is operating in the dual frequency bands simultaneously, significant linearity issues occur. To resolve the problems, a study to find significant intermodulation (IM) products, which increase the third intermodulation (IM3) products most, has been done. Also, an advanced simulation and measurement methodology using three fundamental tones is proposed. An 8-way power divider with dual-band frequency response of 22–29 and 57–64 GHz is designed as a constituent component of the phased-array TX

Novel Approach to Design Ultra Wideband Microwave Amplifiers: Normalized Gain Function Method

In this work, we propose a novel approach called as “Normalized Gain Function (NGF) method” to design low/medium power single stage ultra wide band microwave amplifiers based on linear S parameters of the active device. Normalized Gain Function TNGF is defined as the ratio of T and |S21|^2, desired shape or frequency response of the gain function of the amplifier to be designed and the shape of the transistor forward gain function, respectively. Synthesis of input/output matching networks (IMN/OMN) of the amplifier requires mathematically generated target gain functions to be tracked in two different nonlinear optimization processes. In this manner, NGF not only facilitates a mathematical base to share the amplifier gain function into such two distinct target gain functions, but also allows their precise computation in terms of TNGF=T/|S21|^2 at the very beginning of the design. The particular amplifier presented as the design example operates over 800-5200 MHz to target GSM, UMTS, Wi-Fi and WiMAX applications. An SRFT (Simplified Real Frequency Technique) based design example supported by simulations in MWO (MicroWave Office from AWR Corporation) is given using a 1400mW pHEMT transistor, TGF2021-01 from TriQuint Semiconductor

3-D distributed memory polynomial behavioral model for concurrent dual-band envelope tracking power amplifier linearization

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a new 3-D behavioral model to compensate for the nonlinear distortion arising in concurrent dual-band (DB) Envelope Tracking (ET) Power Amplifiers (PAs). The advantage of the proposed 3-D distributed memory polynomial (3D-DMP) behavioral model, in comparison to the already published behavioral models used for concurrent dual-band envelope tracking PA linearization, is that it requires a smaller number of coefficients to achieve the same linearity performance, which reduces the overall identification and adaptation computational complexity. The proposed 3D-DMP digital predistorter (DPD) is tested under different ET supply modulation techniques. Moreover, further model order reduction of the 3D-DMP DPD is achieved by applying the principal component analysis (PCA) technique. Experimental results are shown considering a concurrent DB transmission of aWCDMA signal at 1.75GHz and a 10-MHz bandwidth LTE signal at 2.1 GHz. The performance of the proposed 3D-DMP DPD is evaluated in terms of linearity, drain power efficiency, and computational complexity.Peer ReviewedPostprint (author's final draft

Compact Digital Predistortion for Multi-band and Wide-band RF Transmitters

This thesis is focusing on developing a compact digital predistortion (DPD) system which costs less DPD added power consumptions. It explores a new theory and techniques to relieve the requirement of the number of training samples and the sampling-rate of feedback ADCs in DPD systems. A new theory about the information carried by training samples is introduced. It connects the generalized error of the DPD estimation algorithm with the statistical properties of modulated signals. Secondly, based on the proposed theory, this work introduces a compressed sample selection method to reduce the number of training samples by only selecting the minimal samples which satisfy the foreknown probability information. The number of training samples and complex multiplication operations required for coefficients estimation can be reduced by more than ten times without additional calculation resource. Thirdly, based on the proposed theory, this thesis proves that theoretically a DPD system using memory polynomial based behavioural modes and least-square (LS) based algorithms can be performed with any sampling-rate of feedback samples. The principle, implementation and practical concerns of the undersampling DPD which uses lower sampling-rate ADC are then introduced. Finally, the observation bandwidth of DPD systems can be extended by the proposed multi-rate track-and-hold circuits with the associated algorithm. By addressing several parameters of ADC and corresponding DPD algorithm, multi-GHz observation bandwidth using only a 61.44MHz ADC is achieved, and demonstrated the satisfactory linearization performance of multi-band and continued wideband RF transmitter applications via extensive experimental tests

Efficient High-Performance Millimeter-Wave Front-End Integrated Circuit Designs and Techniques in SiGe BiCMOS

This dissertation presents various “efficient” design techniques for mm-wave front-end integrated circuits in regards to dc power, bandwidth, and chip size. The ideas, while suitable for different CMOS/BiCMOS processes, were implemented using a 0.18-μm SiGe BiCMOS process. The proposed techniques are validated through the actual implementations of several building blocks constituting two different front-end sections: a V-band OOK/pulse transceiver front-end and a concurrent K-/V-band receiver front-end, where K-band ranges from 18 to 27 GHz and V-band from 40 to 75 GHz. As one of the constituent components in the V-band pulse transmitter, a 60-GHz active OOK/pulse modulator has been designed with an emphasis on the enhancement in the ON/OFF isolation. Having a decent gain (higher than 10 dB), the designed modulator can also be used as a driver stage, which can save the chip area and possibly the dc power consumption compared to the combination of a switch-based passive modulator and a drive amplifier. For the receiver front-end, a wideband V-band low-noise amplifier (LNA) has been designed. Employing a wideband gain shaping technique through two T-type inter-stage matching networks, the designed LNA features very high gain-bandwidth product compared to the conventional gain-staggered wideband amplifier designs for a given dc power consumption. For the concurrent K-/V-band receiver front-end, a low-noise and variable gain stages have been designed. As the first component of the receiver chain, a concurrent dual-band LNA has been designed within a similar footprint required for a single-band amplifier operating either at K- or V-band. The most significant direct intermodulation (IM) product and harmonics are suppressed by a simple rejection network between the input and cascode devices of the 1st stage. This network also plays a crucial role in achieving dual-band input matching through Miller effect. For amplitude control purposes in the RF stage, a variable gain amplifier (VGA) operating concurrently at K- and V-bands has been developed starting from a wideband amplifier design. By replacing the inductors in the wideband design with the transformer-coupled resonators (TCRs), the critical direct IM products can be suppressed without increasing the active chip area. Gain tuning is achieved by conventional current steering, but a new technique is applied to reduce phase variation in the course of gain tuning process, which is one of the most critical concerns, especially in phased array systems

Development of an Encrypted Wireless System for Body Sensor Network Applications

Wireless body area networks (WBAN), also called wireless body sensor networks (WBSN), consist of a collection of wireless sensor nodes used to monitor and assess various human physiological conditions, which can then be used by healthcare professionals to help them make important healthcare decisions. They can be used to prevent disease, help diagnosis a disease, or manage the symptoms of a disease. An extremely important aspect of WBAN is security to protect a patient\u27s healthcare information, as a hacker could potentially cause fatal harm. Current security measures are implemented in software at the MAC layer and higher, not in the physical layer. Previous research demonstrated a chaotic encryption cipher to add a layer of security in the physical layer. This cipher exploits different properties of the Lorenz chaotic system to encrypt and decrypt digital data. Decryption involved synchronizing two chaotic signals to recover original data by sharing a state between the transmitter and receiver. In this thesis, we further develop the encryption system by implementing wireless capabilities. We use two approaches: the first by using commercially available wireless microcontrollers that communicate using Bluetooth Low Energy, and the second by the design and fabrication of a dual-band low noise amplifier (LNA) that can be used in a receiver for WBANs collecting data from implantable and on-the-body sensors. For the first approach, a custom Bluetooth Low Energy profile was created for streaming the analog encrypted signal, and signal processing was done at the receiver side. For the second approach, the LNA operates at the Medical Implant Communication System (MICS) band and the 915 MHz Industrial, Scientific, and Medical (ISM) band simultaneously through dual-band input and output matching networks

Design of efficient microwave power amplifier systems

In the future communication systems, it is of key importance that the transceivers are capable of operating in multiple frequency bands and with complex signals. In this context, the power amplifier is a critical component of the transceiver, since it is responsible for most of the total power consumption in base stations and portable devices. Apart from the power consumption, the design of power amplifier systems must account for multi-band/broadband capabilities, high peak-toaverage power ratio signals and the mismatch effect caused by the various operating conditions. Hence, the design of power amplifier topologies that enhance the total system efficiency and reliability is a challenging task. This PhD dissertation introduces novel power amplifier architectures and solutions for modern communication systems. The contributions of this thesis can be divided in two parts. The first part deals with the study and design of power amplifier systems. It is of major importance that these designs provide linear amplification and operation at multiple frequency bands, which will permit the reduction of the cost and size of the devices. Additionally, we investigate the possibility to harvest the dissipated power from the power amplification process. For the development of the prototypes, lumped-element topologies, transmission line implementation and Substrate Integrated Waveguide (SIW) technology are adopted. In the second part of the thesis, novel matching networks are introduced and their properties are studied. In particular, resistance compression topologies are proposed to overcome the performance degradation associated with the sensitivity of nonlinear devices to environmental changes. These networks can be adopted in modern power amplifier architectures, such as envelope tracking and outphasing energy recovery power amplifier topologies, in order to provide improved performance over a wide range of operating conditions.Es primordial que los transceptores de los futuros sistemas de comunicación sean capaces de operar en múltiples bandas de frecuencia y con señales complejas. En este contexto, el amplificador de potencia es un componente crítico del transceptor dado que su consumo energético supone la mayor parte del consumo tanto de las estaciones base como de los dispositivos móviles. Aparte del consumo energético, los nuevos diseños de sistemas de amplificación de potencia deben considerar aspectos como la capacidad de operar en múltiples bandas o en banda ancha, el uso de señales con alta relación de potencia pico a potencia media (PAPR) y el efecto de desadaptación que aparece bajo las diferentes condiciones de funcionamiento. Por lo tanto, el diseño de nuevas topologías para amplificadores de potencia que mejoren la eficiencia total del sistema y la fiabilidad es una tarea compleja. Esta tesis doctoral presenta nuevas arquitecturas de amplificadores de potencia y soluciones para los sistemas de comunicación modernos. Las contribuciones de esta tesis se pueden dividir en dos partes. La primera parte se centra en el estudio y diseño de sistemas de amplificación de potencia con el fin de proporcionar amplificación lineal y funcionamiento en múltiples bandas de frecuencia, lo que permitirá reducir el coste y tamaño de los dispositivos. Además, se investiga la posibilidad de reutilizar la energía disipada en el proceso de amplificación de potencia. Para el desarrollo de los prototipos, se utilizan topologías hibridas, implementaciones con líneas de transmisión y tecnología de guía de onda integrada en sustrato (SIW). En la segunda parte de la tesis, se proponen redes de adaptación y se estudian sus propiedades. En particular, se proponen topologías de compresión de resistencia para minimizar el efecto que producen en el rendimiento la sensibilidad de los dispositivos no lineales a los cambios ambientales. Estas redes pueden ser utilizadas en arquitecturas modernas de amplificadores de potencia como pueden ser las topologías envelope tracking y outphasing energy recovery con el fin de proporcionar un rendimiento mejorado bajo múltiples condiciones de funcionamiento

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d