Wide-bandwidth high-resolution search for extraterrestrial intelligence

Research accomplished in the following areas is discussed: the antenna configuration; HEMT low-noise amplifiers; the downconverter; the Fast Fourier Transform Array; the backend array; and the backend and workstation

Design techniques to enhance low-power wireless communication soc with reconfigurability and wake up radio

Nowadays, Internet of things applications are increasing, and each end-node has more demanding requirements such as energy efficiency and speed. The thesis proposes a heterogeneous elaboration unit for smart power applications, that consists of an ultra-low-power microcontroller coupled with a small (around 1k equivalent gates) soft-core of embedded FPGA. This digital system is implemented in 90-nm BCD technology of STMicroelectronics, and through the analysis presented in this thesis proves to have good performance in terms of power consumption and latency. The idea is to increase the system performance exploiting the embedded FPGA to managing smart power tasks. For the intended applications, a remarkable computational load is not required, it is just required the implementation of simple finite state machines, since they are event-driven applications. In this way, while the microcontroller deals with other system computations such as high-level communications, the eFPGA can efficiently manage smart power applications. An added value of the proposed elaboration unit is that a soft-core approach is applied to the whole digital system including the eFPGA, and hence, it is portable to different technologies. On the other hand, the configurability improvement has a straightforward drawback of about a 20–27% area overhead. The eFPGA usage to manage smart power applications, allows the system to reduce the required energy per task from about 400 to around 800 times compared to a processor implementation. The eFPGA utilization improves also the latency performance of the system reaching from 8 to 145 times less latency in terms of clock cycles. The thesis also introduces the architecture of a nano-watt wake-up radio integrated circuit implemented in 90-nm BCD technology of STMicroelectronics. The wake-up radio is an auxiliary always-on radio for medium-range applications that allows the IoT end-nodes to drastically reduce the power consumption during the node idle-listening communication phase

Design and development of a remote reconfigurable internet embedded I/O controller

The use of embedded Internet systems is growing rapidly in the manufacturing sector. These systems allow the monitoring and controlling of plant machinery and manufactured items from a remote location via a standard Web interface. In a manufacturing environment, it is inevitable that long running processes will require support for dynamic reconfiguration because, for example, machines may fail, services may be moved or withdrawn and user requirements may change. In such an environment it is essential that the operation and architecture of such processes can be modified to reflect such changes. This research project will present methods and ideas for establishing a reconfigurable remote system by using standard 8-bit microcontrollers and reconfigurable hardware. It will allow a manufacturing process to be modified and changed within minutes without even having to be physically present at the location where the process is running

FPGA implementation of a frame delay

The objective of this thesis is to investigate the applicability of Field Programmable Gate Arrays (FPGAs) for frame delay implementation. FPGAs are programmable devices that can be directly configured by the end user without the use of an integrated circuit fabrication facility. They offer the designer the benefits of custom hardware, eliminating high development costs and manufacturing time. Frame delays are easier to realize using R/W memory where data is written into the memory and read out for each frame. FPGAs are used in a Quartus II environment as it is easy to perform frame delay implementation using schematic entry procedure. Since FPGAs use look-up tables as configurable logic blocks, they are considered as an appropriate choice for frame delay based designs

Implementation of Viterbi decoder on Xilinx XC4005XL FPGA

The Viterbi decoding algorithm is used to decode convolutional codes and is found in many systems that receive digital data that might contain errors. The use of error-correcting codes has proven tobe an effective way to overcome data corruption in digital communication channels. In previous works, researchers describe the Viterbi Algorithm, but the accuracy does not exceed 10% of data points. Also, a lot of previous works do not follow IEEE 802.16 new specifications. Viterbi decoders are generally implemented using programmable digital signal processors (DSPs) or special purpose chip sets and application-specific integrated circuits (ASICs). Here, we aim to implement such decoder on an FPGA. In This paper, we provide a more accurate Viterbi decoder according to IEEE 802.16 specifications. We used VHDL hardware description language to implement the algorithm. We also used OrCAD Capture V9.1 to compile, synthesize, and simulate our code. IEEE 802.16 standard specifies the air interface of fixed point-to-multipoint broadband wireless access (BWA) systems providing multiple services. This standard is intended to enable rapid worldwide deployment of broadband wireless access products. The new IEEE 802.16 specifications require a Viterbi block decoder with constraint length of 3, traceback length of 32, and minimum throughput requirement of 44.8 Mbps. The Implementation parameters for the decoder have been determined through simulation and the decoder has been implemented on a Xilinx XC4005XL FPGA

Signal Processing for an Autonomous Underwater Vehicle: an FPGA approach

The idea of this thesis comes out from the participation of the University of Central Florida to the Annual International Autonomous Underwater Vehicle Competition of 2007. The objective of this competition is to make the AUV to accomplish to a specific route. A part of this route expects the AUV to detect a ping and following it as a source. The objective of this thesis is to improve the performance of this trajectory tracking. A Field Programmable Logic Array will be used to perform an effective Digital Signal Processing

High integrity hardware-software codesign

Programmable logic devices (PLDs) are increasing in complexity and speed, and are being used as important components in safety-critical systems. Methods for developing high-integrity software for these systems are well-known, but this is not true for programmable logic. We propose a process for developing a system incorporating software and PLDs, suitable for safety critical systems of the highest levels of integrity. This process incorporates the use of Synchronous Receptive Process Theory as a semantic basis for specifying and proving properties of programs executing on PLDs, and extends the use of SPARK Ada from a programming language for safety-critical systems software to cover the interface between software and programmable logic. We have validated this approach through the specification and development of a substantial safety-critical system incorporating both software and programmable logic components, and the development of tools to support this work. This enables us to claim that the methods demonstrated are not only feasible but also scale up to realistic system sizes, allowing development of such safety-critical software-hardware systems to the levels required by current system safety standards