DESIGN AUTOMATION FOR CARBON NANOTUBE CIRCUITS CONSIDERING PERFORMANCE AND SECURITY OPTIMIZATION

As prevailing copper interconnect technology advances to its fundamental physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Carbon nanotube (CNT) interconnects have emerged as promising replacement materials for copper interconnects due to their superior conductivity. Buffer insertion for CNT interconnects is capable of improving circuit timing of signal nets with limited buffer deployment. However, due to the imperfection of fabricating long straight CNT, there exist significant unidimensional-spatially correlated variations on the critical CNT geometric parameters such as the diameter and density, which will affect the circuit performance. This dissertation develops a novel timing driven buffer insertion technique considering unidimensional correlations of variations of CNT. Although the fabrication variations of CNTs are not desired for the circuit designs targeting performance optimization and reliability, these inherent imperfections make them natural candidates for building highly secure physical unclonable function (PUF), which is an advanced hardware security technology. A novel CNT PUF design through leveraging Lorenz chaotic system is developed and we show that it is resistant to many machine learning modeling attacks. In summary, the studies in this dissertation demonstrate that CNT technology is highly promising for performance and security optimizations in advanced VLSI circuit design

In-memory computing with emerging memory devices: Status and outlook

Supporting data for "In-memory computing with emerging memory devices: status and outlook", submitted to APL Machine Learning

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors

Metal-oxide semiconductor field-effect transistor (MOSFET) scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. After forty years of advances in integrated circuit (IC) technology, the scaling of silicon (Si) MOSFET has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. The latest technological advancement has led to a low power, high-density and high-speed generation of processor. Nevertheless, the scaling of the Si MOSFET below 22 nm may soon meet its’ fundamental physical limitations. This threshold makes the possible use of novel devices and structures such as carbon nanotube field-effect transistors (CNTFETs) and graphene nanoribbon field-effect transistors (GNRFETs) for future nanoelectronics. The investigation explores the potential of these amazing carbon structures that exceed MOSFET capabilities in term of speed, scalability and power consumption. The research findings demonstrate the potential integration of carbon based technology into existing ICs. In particular, a simulation program with integrated circuit emphasis (SPICE) model for CNTFET and GNRFET in digital logic applications is presented. The device performance of these circuit models and their design layout are then compared to 45 nm and 90 nm MOSFET for benchmarking. It is revealed through the investigation that CNT and GNR channels can overcome the limitations imposed by Si channel length scaling and associated short channel effects while consuming smaller channel area at higher current density

Preparation and characterization of Carbon Nanotube based vertical interconnections for integrated circuits: Preparation and characterization of Carbon Nanotube based verticalinterconnections for integrated circuits

(ULSI) causes an increase of the resistance of the wiring system by increased scattering of electrons at side walls and grain boundaries in the state of the art Cu technology, which increases the RC delay of the interconnect system and thus degrades the performance of the device. The outstanding properties of carbon nanotubes (CNT) such as a large mean free path, a high thermal conductance and a large resistance against electromigration make them an ideal candidate to replace Cu in future feature nodes. The present thesis contributes to the preparation and properties of CNT based vertical interconnections (vias). In addition, all processes applied during the fabrication are compatible to ULSI and an interface between CNT based vias and a Cu metallization is studied. The methodology for the evaluation of CNT based vias is improved; it is highlighted that by measuring the resistance of one multiwall CNT and taking into account the CNT density, the performance of the CNT based vias can be predicted accurately. This provides the means for a systematic evaluation of different integration procedures and materials. The lowest contact resistance is obtained for carbide forming metals, as long as oxidation during the integration is avoided. Even though metal-nitrides exhibit an enhanced contact resistance, they are recommended to be used at the bottom metallization in order to minimize the oxidation of the metal-CNT contact during subsequent processing steps. Overall a ranking for the materials from the lowest to the highest contact resistance is obtained: Ta < Ti < TaN < TiN « TiO2 « Ta2O5 Furthermore the impact of post CNT growth procedures as chemical mechanical planarization, HF treatment and annealing procedures after the CNT based via fabrication are evaluated. The conductance of the incorporated CNTs and the applicable electrical transport regime relative to the CNT quality and the CNT length is discussed. In addition, a strong correlation between the temperature coefficient of resistance and the initial resistance of the CNT based vias at room temperature has been observed.Die kontinuierliche Miniaturisierung der charakteristischen Abmessungen in hochintegrierten Schaltungen (ULSI) verursacht einen Anstieg des Widerstandes im Zuleitungssystem aufgrund der erhöhten Streuung von Elektronen an Seitenwänden und Korngrenzen in der Cu-Technologie, wodurch die Verzögerungszeit des Zuleitungssystems ansteigt. Die herausragenden Eigenschaften von Kohlenstoffnanoröhren (CNT), wie eine große mittlere freie Weglänge, hohe thermische Leitfähigkeit und eine starke Resistenz gegenüber Elektromigration machen diese zu einem idealen Kandidaten, um Cu in zukünftigen Technologiegenerationen zu ersetzen. Die vorliegende Arbeit beschreibt die Herstellung und daraus resultierenden Eigenschaften von Zwischenebenenkontakten (Vias) basierend auf CNTs. Alle verwendeten Prozessierungsschritte sind kompatibel mit der Herstellung von hochintegrierten Schaltkreisen und eine Schnittstelle zwischen den CNT Vias und einer Cu-Metallisierung ist vorhanden. Insbesondere das Verfahren zur Evaluierung von CNT Vias wurde durch den Einsatz verschiedener Methoden verbessert. Insbesondere soll hervorgehoben werden, dass durch die Messung des Widerstandes eines einzelnen CNTs, bei bekannter CNT Dichte, der Via Widerstand sehr genau vorausgesagt werden kann. Dies ermöglicht eine systematische Untersuchung des Einflusses der verschiedenen Prozessschritte und der darin verwendeten Materialien auf den Via Widerstand. Der niedrigste Kontaktwiderstand wird für Karbidformierende Metalle erreicht, solange Oxidationsprozesse ausgeschlossen werden können. Obwohl Metallnitride einen höheren Kontaktwiderstand aufweisen, sind diese für die Unterseitenmetallisierung zu empfehlen, da dadurch die Oxidation der leitfähigen Schicht minimiert wird. Insgesamt kann eine Reihenfolge beginnend mit dem niedrigsten zum höchsten Kontaktwiderstand aufgestellt werden: Ta < Ti < TaN < TiN « TiO2 « Ta2O5 Desweiteren wurde der Einfluss von Verfahren nach dem CNTWachstum wie die chemischmechanische Planarisierung, eine HF Behandlung und einer Temperaturbehandlung evaluiert, sowie deren Einfluss auf die elektrischen Parameter des Vias untersucht. Die Leitfähigkeit der integrierten CNTs und die daraus resultierenden elektrischen Transporteigenschaften in Abhängigkeit der CNT Qualität und Länge werden besprochen. Ebenso wird die starke Korrelation zwischen dem Temperaturkoeffizienten des elektrischen Widerstandes und des Ausgangswiderstandes der CNT basierten Vias bei Raumtemperatur diskutiert

Time-Resolved Photoluminescence and Elastic White Light Scattering Studies of Individual Carbon Nanotubes and Optical Characterization of Oxygen Plasma Treated Graphene

In the course of this work the excited state dynamics of individual single-walled carbon nanotubes (SWCNTs) were studied by a combination of confocal PL spectroscopy and time correlated single photon counting (TCSPC) measurements. Nonradiative decay channels dominate the excited state dynamics of SWCNTs leading to low photoluminescence (PL) quantum yields and PL decay times on the picosecond timescale. Knowledge about the microscopic nature of these decay channels is crucial to improve the material properties. The measurements on the single nanotube level revealed large tube-to-tube variations of PL decay times, which could be attributed to different defect densities for different tubes. For the present SWCNT material the PL decay times only depend weakly on the nanotube length. SWCNT material synthesized by using a cobalt-molybdenum catalyst (CoMoCAT) systematically display short monoexponential PL decays, while the PL decay dynamics of SWCNTs produced high pressure decomposition of carbon monoxide process (HiPco) is either mono or biexponential depending on the respective local environment of the nanotube. The transition from a bi- to monoexponential PL decay can be explained by synthesis-dependent differences in defect densities. This defect related nonradiative decay channels reduce the amplitude of one decay component below the experimental detection limit. It is further shown, that photo-induced defects and gold atoms adsorbed to the sidewalls of SWCNTs are shown to alter the PL properties of individual SWCNTs. Additional low-energy PL satellite bands arise in the spectra. Their origin can be attributed to emission from nominally dark excitons which are ”brightened” due to defect facilitated mixing of intrinsic states with different parity/spin. The role of defects in the brightening process was investigated by time-resolved PL measurements and complementary Raman spectroscopy. Based on its energy separation and the unusually slow PL decay dynamics the lowest energy satellite band can be assigned to the radiative recombination of a triplet exciton. In a second project a common-path interference scattering approach (iSCAT) utilizing a conventional inverted laser scanning confocal microscope combined with a photonic crystal fibre as a supercontinuum white light source is successfully tested for its capabilities for elastic scattering imaging and spectroscopy of individual SWCNTs. Finally, it is shown that single layer graphene can selectively be turned luminescent upon exposure to a mild oxygen plasma. The treatment leads to a strong and spatially uniform PL which is characterized by a single, broad PL band extending from the visible to the near infrared spectral region. The analysis of the defect related Raman I(D)/I(G) intensity ratio indicates the formation of nanometer sized islands for which the sp2 conjugated lattice of graphene is still preserved. Emission of quantum confined states within these islands is discussed as a possible origin of the PL

NASA Tech Briefs, September 2010

Topics covered include: Instrument for Measuring Thermal Conductivity of Materials at Low Temperatures; Multi-Axis Accelerometer Calibration System; Pupil Alignment Measuring Technique and Alignment Reference for Instruments or Optical Systems; Autonomous System for Monitoring the Integrity of Composite Fan Housings; A Safe, Self-Calibrating, Wireless System for Measuring Volume of Any Fuel at Non-Horizontal Orientation; Adaptation of the Camera Link Interface for Flight-Instrument Applications; High-Performance CCSDS Encapsulation Service Implementation in FPGA; High-Performance CCSDS AOS Protocol Implementation in FPGA; Advanced Flip Chips in Extreme Temperature Environments; Diffuse-Illumination Systems for Growing Plants; Microwave Plasma Hydrogen Recovery System; Producing Hydrogen by Plasma Pyrolysis of Methane; Self-Deployable Membrane Structures; Reactivation of a Tin-Oxide-Containing Catalys; Functionalization of Single-Wall Carbon Nanotubes by Photo-Oxidation; Miniature Piezoelectric Macro-Mass Balance; Acoustic Liner for Turbomachinery Applications; Metering Gas Strut for Separating Rocket Stages; Large-Flow-Area Flow-Selective Liquid/Gas Separator; Counterflowing Jet Subsystem Design; Water Tank with Capillary Air/Liquid Separation; True Shear Parallel Plate Viscometer; Focusing Diffraction Grating Element with Aberration Control; Universal Millimeter-Wave Radar Front End; Mode Selection for a Single-Frequency Fiber Laser; Qualification and Selection of Flight Diode Lasers for Space Applications; Plenoptic Imager for Automated Surface Navigation; Maglev Facility for Simulating Variable Gravity; Hybrid AlGaN-SiC Avalanche Photodiode for Deep-UV Photon Detection; High-Speed Operation of Interband Cascade Lasers; 3D GeoWall Analysis System for Shuttle External Tank Foreign Object Debris Events; Charge-Spot Model for Electrostatic Forces in Simulation of Fine Particulates; Hidden Statistics Approach to Quantum Simulations; Reconstituted Three-Dimensional Interactive Imaging; Determining Atmospheric-Density Profile of Titan; Digital Microfluidics Sample Analyzer; Radiation Protection Using Carbon Nanotube Derivatives; Process to Selectively Distinguish Viable from Non-Viable Bacterial Cells; and TEAMS Model Analyzer

High Performance Optical Transmitter Ffr Next Generation Supercomputing and Data Communication

High speed optical interconnects consuming low power at affordable prices are always a major area of research focus. For the backbone network infrastructure, the need for more bandwidth driven by streaming video and other data intensive applications such as cloud computing has been steadily pushing the link speed to the 40Gb/s and 100Gb/s domain. However, high power consumption, low link density and high cost seriously prevent traditional optical transceiver from being the next generation of optical link technology. For short reach communications, such as interconnects in supercomputers, the issues related to the existing electrical links become a major bottleneck for the next generation of High Performance Computing (HPC). Both applications are seeking for an innovative solution of optical links to tackle those current issues. In order to target the next generation of supercomputers and data communication, we propose to develop a high performance optical transmitter by utilizing CISCO Systems®\u27s proprietary CMOS photonic technology. The research seeks to achieve the following outcomes: 1. Reduction of power consumption due to optical interconnects to less than 5pJ/bit without the need for Ring Resonators or DWDM and less than 300fJ/bit for short distance data bus applications. 2. Enable the increase in performance (computing speed) from Peta-Flop to Exa-Flops without the proportional increase in cost or power consumption that would be prohibitive to next generation system architectures by means of increasing the maximum data transmission rate over a single fiber. 3. Explore advanced modulation schemes such as PAM-16 (Pulse-Amplitude-Modulation with 16 levels) to increase the spectrum efficiency while keeping the same or less power figure. This research will focus on the improvement of both the electrical IC and optical IC for the optical transmitter. An accurate circuit model of the optical device is created to speed up the performance optimization and enable co-simulation of electrical driver. Circuit architectures are chosen to minimize the power consumption without sacrificing the speed and noise immunity. As a result, a silicon photonic based optical transmitter employing 1V supply, featuring 20Gb/s data rate is fabricated. The system consists of an electrical driver in 40nm CMOS and an optical MZI modulator with an RF length of less than 0.5mm in 0.13&mu m SOI CMOS. Two modulation schemes are successfully demonstrated: On-Off Keying (OOK) and Pulse-Amplitude-Modulation-N (PAM-N N=4, 16). Both versions demonstrate signal integrity, interface density, and scalability that fit into the next generation data communication and exa-scale computing. Modulation power at 20Gb/s data rate for OOK and PAM-16 of 4pJ/bit and 0.25pJ/bit are achieved for the first time of an MZI type optical modulator, respectively

Neuroglia

This book is a compiled version of the journal Neuroglia. It was a peer-review Open Access journal by MDPI that investigated a wide range of glia related topics. Now the journal is published as a section of the journal Brain Sciences, with a new section Editor-in-Chief Prof. Sergey Kasparov