Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add

The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that they are entering now. Floating-point (FP) fused multiply-add (FMA), being a functional unit with high power consumption, deserves special attention. Although clock gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector FMA units (VFUs). These techniques ensure power savings without jeopardizing the timing. We evaluate the proposed techniques using both synthetic and “real-world” application-based benchmarking. Using vector masking and vector multilane-aware clock gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector FP instructions. Finally, when evaluating all techniques together, using “real-world” benchmarking, the power reductions are up to 80%. Additionally, in accordance with processor design trends, we perform this research in a fully parameterizable and automated fashion.The research leading to these results has received funding from the RoMoL ERC Advanced Grant GA 321253 and is supported in part by the European Union (FEDER funds) under contract TTIN2015-65316-P. The work of I. Ratkovic was supported by a FPU research grant from the Spanish MECD.Peer ReviewedPostprint (author's final draft

Automation and Control Architecture for Hybrid Pipeline Robots

The aim of this research project, towards the automation of the Hybrid Pipeline Robot (HPR), is the development of a control architecture and strategy, based on reconfiguration of the control strategy for speed-controlled pipeline operations and self-recovering action, while performing energy and time management. The HPR is a turbine powered pipeline device where the flow energy is converted to mechanical energy for traction of the crawler vehicle. Thus, the device is flow dependent, compromising the autonomy, and the range of tasks it can perform. The control strategy proposes pipeline operations supervised by a speed control, while optimizing the energy, solved as a multi-objective optimization problem. The states of robot cruising and self recovering, are controlled by solving a neuro-dynamic programming algorithm for energy and time optimization, The robust operation of the robot includes a self-recovering state either after completion of the mission, or as a result of failures leading to the loss of the robot inside the pipeline, and to guaranteeing the HPR autonomy and operations even under adverse pipeline conditions Two of the proposed models, system identification and tracking system, based on Artificial Neural Networks, have been simulated with trial data. Despite the satisfactory results, it is necessary to measure a full set of robot’s parameters for simulating the complete control strategy. To solve the problem, an instrumentation system, consisting on a set of probes and a signal conditioning board, was designed and developed, customized for the HPR’s mechanical and environmental constraints. As a result, the contribution of this research project to the Hybrid Pipeline Robot is to add the capabilities of energy management, for improving the vehicle autonomy, increasing the distances the device can travel inside the pipelines; the speed control for broadening the range of operations; and the self-recovery capability for improving the reliability of the device in pipeline operations, lowering the risk of potential loss of the robot inside the pipeline, causing the degradation of pipeline performance. All that means the pipeline robot can target new market sectors that before were prohibitive

Index to NASA Tech Briefs, 1975

This index contains abstracts and four indexes--subject, personal author, originating Center, and Tech Brief number--for 1975 Tech Briefs

Implementation and Analysis of Direct Torque Control for Permanent Magnet Synchronous Motor Using Gallium Nitride based Inverter

Permanent magnet synchronous machines (PMSMs) attract considerable attention in various industrial applications, such as electric and hybrid electric vehicles, due to their high efficiency and high-power density. In this thesis, the mathematical model of PMSM and two popular control strategies, field-oriented control (FOC) and direct torque control (DTC), are analyzed and compared. The results demonstrated that the DTC has better dynamic response in comparison to FOC. Moreover, DTC can eliminate the use of position sensor, which will save the cost of the PMSM drive system. Therefore, this thesis focuses on the design and implementation of high-performance DTC for PMSMs with a Gallium Nitride (GaN) based high switching frequency motor drive. First, the characteristics and operation principles of a PMSM are introduced. Then, the mathematical models of a PMSM under different coordinate systems are investigated. Consequently, a PMSM model is developed based on the dq rotating reference frame and implemented in the MATLAB/Simulink for validation. Two advanced PMSM control strategies, FOC and DTC, are investigated and compared in terms of control performance through comprehensive simulation studies and the results demonstrate that DTC has better dynamic performance. Conventional DTC contributes to higher torque ripple in the PMSM due to the limited switching frequency in a conventional semiconductor-based motor drive, which inevitably deteriorates the drive performance. Therefore, this thesis aims to reduce the torque ripple in the DTC based PMSM drive by using the new generation wide bandgap switching devices. More specifically, DTC is improved by using the optimized space vector pulse width modulation strategy and a higher switching frequency contributed by the GaN based motor drive. Finally, the proposed DTC-SVM based PMSM control strategy is implemented on the digital signal processor (DSP) and evaluated on the laboratory GaN based PMSM drive. Both the simulation and experimental results show that the proposed improvement in the DTC can further improve the PMSM drive performance

Homogeneous and heterogeneous MPSoC architectures with network-on-chip connectivity for low-power and real-time multimedia signal processing

Two multiprocessor system-on-chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC) infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices