Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement

Towards integrating chalcogenide based phase change memory with silicon microelectronics

The continued dominance of floating gate technology as the premier non-volatile memory (NVM) technology is expected to hit a roadblock due to issues associated with its inability to catch up with CMOS scaling. The uncertain future of floating gate memory has led to a host of unorthodox NVM technologies to surface as potential heirs. Among the mix is phase change memory (PCM), which is a non-volatile, resistance variable, memory technology wherein the state of the memory bit is defined by the resistance of the memory material. This research study examines novel, bilayer chalcogenide based materials composed of Ge-chalcogenide (GeTe or Ge2Se3) and Sn-chalcogenide (SnTe or SnSe) for phase change memory applications and explores their integration with CMOS technology. By using a layered arrangement, it is possible to induce phase change response in materials, which normally do not exhibit such behavior, and thus form new materials which may have lower threshold voltage and programming current requirements. Also, through the incorporation of a metal containing layer, the phase transition characteristics of the memory layer can be tailored in order to obtain in-situ, a material with optimized phase change properties. Using X-ray diffraction (XRD) and time resolved XRD, it has been demonstrated that stacked phase change memory films exhibit both structural and compositional dependency with annealing temperature. The outcome of the structural transformation of the bottom layer, is an annealing temperature dependent residual stress. By the incorporation of a Sn layer, the phase transition characteristics of Ge-chalcogenide thin films can be tuned. Clear evidence of thermally induced Ge, Sn and chalcogen inter-diffusion, has been discerned via transmission electron microscopy and parallel electron energy loss spectroscopy. The presence of Al2O3 as capping layer has been found to mitigate volatilization and metallic Sn phase separation at high temperatures. Two terminal PCM cells employing these bilayers have been designed, fabricated and tested. All devices exhibit threshold switching and memory switching behavior. By the application of suitable voltage programming pulses, RESET state switching can be accomplished in these devices, thus demonstrating single bit memory functionality. A process for integrating bilayer PCM technology with 2 µm CMOS has been designed and developed. The baseline RIT CMOS process has been modified to incorporate 12 levels of photolithography, 3 levels of metal and the addition of PCM as a BEOL process. On electrical testing, NMOS connected PCM devices exhibit switching behavior. The effect of the state (SET/RESET) of the series connected PCM cell on the drain current of the NMOS has also been investigated. It is determined that threshold switching of the PCM cell is essential in order to observe any change in MOS drain current with variation in drain voltage. Thus, successful integration of bilayer PCM with CMOS has been demonstrated

Special Topics in Information Technology

This open access book presents thirteen outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the thirteen best theses defended in 2020-21 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists

Special Topics in Information Technology

This open access book presents thirteen outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the thirteen best theses defended in 2020-21 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists

A novel low-temperature growth method of silicon structures and application in flash memory.

Flash memories are solid-state non-volatile memories. They play a vital role especially in information storage in a wide range of consumer electronic devices and applications including smart phones, digital cameras, laptop computers, and satellite navigators. The demand for high density flash has surged as a result of the proliferation of these consumer electronic portable gadgets and the more features they offer – wireless internet, touch screen, video capabilities. The increase in the density of flash memory devices over the years has come as a result of continuous memory cell-size reduction. This size scaling is however approaching a dead end and it is widely agreed that further reduction beyond the 20 nm technological node is going to be very difficult, as it would result to challenges such as cross-talk or cell-to-cell interference, a high statistical variation in the number of stored electrons in the floating gate and high leakage currents due to thinner tunnel oxides. Because of these challenges a wide range of solutions in form of materials and device architectures are being investigated. Among them is three-dimensional (3-D) flash, which is widely acclaimed as the ideal solution, as they promise the integration of long-time retention and ultra-high density cells without compromising device reliability. However, current high temperature (>600 °C) growth techniques of the Polycrystalline silicon floating gate material are incompatible with 3-D flash memory; with vertically stacked memory layers, which require process temperatures to be ≤ 400 °C. There already exist some low temperature techniques for producing polycrystalline silicon such as laser annealing, solid-phase crystallization of amorphous silicon and metal-induced crystallization. However, these have some short-comings which make them not suitable for use in 3-D flash memory, e.g. the high furnace annealing temperatures (700 °C) in solid-phase crystallization of amorphous silicon which could potentially damage underlying memory layers in 3-D flash, and the metal contaminants in metal-induced crystallization which is a potential source of high leakage currents. There is therefore a need for alternative low temperature techniques that would be most suitable for flash memory purposes. With reference to the above, the main objective of this research was to develop a novel low temperature method for growing silicon structures at ≤ 400 °C. This thesis thus describes the development of a low-temperature method for polycrystalline silicon growth and the application of the technique in a capacitor-like flash memory device. It has been demonstrated that silicon structures with polycrystalline silicon-like properties can be grown at ≤ 400 °C in a 13.56 MHz radio frequency (RF) plasma-enhanced chemical vapour deposition (PECVD) reactor with the aid of Nickel Formate Dihydrate (NFD). It is also shown that the NFD coated on the substrates, thermally decomposes in-situ during the deposition process forming Ni particles that act as nucleation and growth sites of polycrystalline silicon. Silicon films grown by this technique and without annealing, have exhibited optical band gaps of ~ 1.2 eV compared to 1.78 eV for films grown under identical conditions but without the substrate being coated. These values were determined from UV-Vis spectroscopy and Tauc plots. These optical band gaps correspond to polycrystalline silicon and amorphous silicon respectively, meaning that the films grown on NFD-coated substrates are polycrystalline silicon while those grown on uncoated substrates remain amorphous. Moreover, this novel technique has been used to fabricate a capacitor-like flash memory that has exhibited hysteresis width corresponding to charge storage density in the order of 1012 cm-2 with a retention time well above 20 days for a device with silicon films grown at 300 °C. Films grown on uncoated films have not exhibit any significant hysteresis, and thus no flash memory-like behaviour. Given that all process temperatures throughout the fabrication of the devices are less than 400 °C and that no annealing of any sort was done on the material and devices, this growth method is thermal budget efficient and meets the crucial process temperature requirements of 3-D flash memory. Furthermore, the technique is glass compatible, which could prove a major step towards the acquisition of flash memory-integrated systems on glass, as well as other applications requiring low temperature polycrystalline silicon

낸드플래시 메모리 오류정정을 위한 고성능 LDPC 복호방법 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 성원용.반도체 공정의 미세화에 따라 비트 에러율이 증가하는 낸드 플래시 메모리에서 고성능 에러 정정 방법은 필수적이다. Low-density parity-check (LDPC) 부호와 같은 연판정 에러 정정 부호는 뛰어난 에러 정정 성능을 보이지만, 높은 구현 복잡도로 인해 플래시 메모리 시스템에 적용되기 힘든 단점이 있다. 본 논문에서는 LDPC 부호의 효율적인 복호를 위해 고성능 메시지 전파 스케줄링 방법과 저 복잡도 복호 알고리즘을 제안한다. 특히 finite geometry (FG) LDPC 부호에 대한 효율적인 디코더 아키텍쳐를 제안하며, 구현된 디코더를 이용하여 낸드 플래시 메모리에 대해 연판정 복호시의 에너지 소모량에 대해 연구한다. 본 논문의 첫 번째 부분에서는 동적 스케줄링 (informed dynamic scheduling, IDS) 알고리즘의 성능향상 방법에 대해 연구한다. 이를 위해 우선 기존의 가장 빠른 수렴 속도를 보이는 IDS 알고리즘인 레지듀얼 신뢰 전파 (residual belief propagation, RBP) 알고리즘의 동작 특성을 분석하고, 이를 바탕으로 특정 노드에 메시지 갱신이 집중되는 것을 방지하여 RBP 알고리즘의 수렴속도를 증가시킨 improved RBP (iRBP) 알고리즘을 제안한다. 또한 iRBP의 뛰어난 수렴속도와 기존의 NS 알고리즘의 우수한 에러 정정 능력을 모두 갖춘 신드롬 기반의 혼합 스케줄링 (mixed scheduling) 방법을 제안한다. 끝으로 다양한 부호율의 LDPC 부호에 대한 모의실험을 통해 제안된 신드롬 기반의 혼합 스케줄링 방법이 본 논문에서 시험된 다른 모든 스케줄링 알고리즘의 성능을 능가함을 확인하였다. 논문의 두 번째 부분에서는 복호 실패시 많은 비트 에러를 발생시키는 a posteriori probability (APP) 알고리즘의 개선 방안에 방안을 제안한다. 또한 빠른 수렴속도와 우수한 에러 마루 (error-floor) 성능으로 데이터 저장장치에 적합한 FG-LDPC 부호에 대해 제안된 알고리즘이 적용된 하드웨어 아키텍처를 제안하였다. 제안된 아키텍처는 높은 노드 가중치를 가지는 FG-LDPC 부호에 적합하도록 쉬프트 레지스터 (shift registers)와 SRAM 기반의 혼합 구조를 채용하며, 높은 처리량을 얻기 위해 파이프라인된 병렬 아키텍처를 사용한다. 또한 메모리 사용량을 줄이기 위해 세 가지의 메모리 용량 감소 기법을 적용하며, 전력 소비를 줄이기 위해 두 가지의 저전력 기법을 제안한다. 본 제안된 아키텍처는 부호율 0.96의 (68254, 65536) Euclidean geometry LDPC 부호에 대해 0.13-um CMOS 공정에서 구현하였다. 마지막으로 본 논문에서는 연판정 복호가 적용된 낸드 플래시 메모리 시스템의 에너지 소모를 낮추는 방법에 대해 제안한다. 연판정 기반의 에러 정정 알고리즘은 높은 성능을 보이지만, 이는 플래시 메모리의 센싱 수와 에너지 소모를 증가 시키는 단점이 있다. 본 연구에서는 앞서 구현된 LDPC 디코더가 채용된 낸드 플래시 메모리 시스템의 에너지 소모를 분석하고, LDPC 디코더와 BCH 디코더 간의 칩 사이즈와 에너지 소모량을 비교하였다. 이와 더불어 본 논문에서는 LDPC 디코더를 이용한 센싱 정밀도 결정 방법을 제안한다. 본 연구를 통해 제안된 복호 및 스케줄링 알고리즘, VLSI 아키텍쳐, 그리고 읽기 정밀도 결정 방법을 통해 낸드 플래시 메모리 시스템의 에러 정정 성능을 극대화 하고 에너지 소모를 최소화 할 수 있다.High-performance error correction for NAND flash memory is greatly needed because the raw bit error rate increases as the semiconductor geometry shrinks for high density. Soft-decision error correction, such as low-density parity-check (LDPC) codes, offers high performance but their implementation complexity hinders wide adoption to consumer products. This dissertation proposes two high-performance message-passing schedules and a low-complexity decoding algorithm for LDPC codes. In particular, an efficient decoder architecture for finite geometry (FG) LDPC codes is proposed, and the energy consumption of soft-decision decoding for NAND flash memory is analyzed. The first part of this dissertation is devoted to improving the informed dynamic scheduling (IDS) algorithms. We analyze the behavior of the residual belief propagation (RBP), which is the fastest IDS algorithm, and develop an improved RBP (iRBP) by avoiding the concentration of message updates at a particular node. We also study the syndrome-based mixed scheduling of the iRBP and the node-wise scheduling (NS). The proposed mixed scheduling outperforms all other scheduling methods tested in this work. The next part of this dissertation is to develop a conditional variable node update scheme for the a posteriori probability (APP) algorithm. The developed algorithm is robust to decoding failures and can reduce the dynamic power consumption by lowering switching activities in the LDPC decoder. To implement the developed algorithm, we propose a memory-efficient pipelined parallel architecture for LDPC decoding. The architecture employs FG-LDPC codes that not only show fast convergence speed and good error-floor performance but also perform well with iterative decoding algorithms, which is especially suitable for data storage devices. We also developed a rate-0.96 (68254, 65536) Euclidean geometry LDPC code and implemented the proposed architecture in 0.13-um CMOS technology. This dissertation also covers low-energy error correction of NAND flash memory through soft-decision decoding. The soft-decision-based error correction algorithms show high performance, but they demand an increased number of flash memory sensing operations and consume more energy for memory access. We examine the energy consumption of a NAND flash memory system equipping an LDPC code-based soft-decision error correction circuit. The sum of energy consumed at NAND flash memory and the LDPC decoder is minimized. In addition, the chip size and energy consumption of the decoder were compared with those of two Bose-Chaudhuri-Hocquenghem (BCH) decoding circuits showing the comparable error performance and the throughput. We also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. This dissertation is intended to develop high-performance and low-power error correction circuits for NAND flash memory by studying improved decoding and scheduling algorithms, VLSI architecture, and a read precision selection method.1 Introduction 1 1.1 NAND Flash Memory 1 1.2 LDPC Codes 4 1.3 Outline of the Dissertation 6 2 LDPC Decoding and Scheduling Algorithms 8 2.1 Introduction 8 2.2 Decoding Algorithms for LDPC Codes 10 2.2.1 Belief Propagation Algorithm 10 2.2.2 Simplified Belief Propagation Algorithms 12 2.3 Message-Passing Schedules for Decoding of LDPC Codes 15 2.3.1 Static Schedules 15 2.3.2 Dynamic Schedules 17 3 Improved Dynamic Scheduling Algorithms for Decoding of LDPC Codes 22 3.1 Introduction 22 3.2 Improved Residual Belief Propagation Algorithm 23 3.3 Syndrome-Based Mixed Scheduling of iRBP and NS 26 3.4 Complexity Analysis and Simulation Results 28 3.4.1 Complexity Analysis 28 3.4.2 Simulation Results 29 3.5 Concluding Remarks 33 4 A Pipelined Parallel Architecture for Decoding of Finite-Geometry LDPC Codes 36 4.1 Introduction 36 4.2 Finite-Geometry LDPC Codes and Conditional Variable Node Update Algorithm 38 4.2.1 Finite-Geometry LDPC codes 38 4.2.2 Conditional Variable Node Update Algorithm for Fixed-Point Normalized APP-Based Algorithm 40 4.3 Decoder Architecture 46 4.3.1 Baseline Sequential Architecture 46 4.3.2 Pipelined-Parallel Architecture 54 4.3.3 Memory Capacity Reduction 57 4.4 Implementation Results 60 4.5 Concluding Remarks 64 5 Low-Energy Error Correction of NAND Flash Memory through Soft-Decision Decoding 66 5.1 Introduction 66 5.2 Energy Consumption of Read Operations in NAND Flash Memory 67 5.2.1 Voltage Sensing Scheme for Soft-Decision Data Output 67 5.2.2 LSB and MSB Concurrent Access Scheme for Low-Energy Soft-Decision Data Output 72 5.2.3 Energy Consumption of Read Operations in NAND Flash Memory 73 5.3 The Performance of Soft-Decision Error Correction over a NAND Flash Memory Channel 76 5.4 Hardware Performance of the (68254, 65536) LDPC Decoder 81 5.4.1 Energy Consumption of the LDPC Decoder 81 5.4.2 Performance Comparison of the LDPC Decoder and Two BCH Decoders 83 5.5 Low-Energy Error Correction Scheme for NAND Flash Memory 87 5.5.1 Optimum Precision for Low-Energy Decoding 87 5.5.2 Iteration Count-Based Precision Selection 90 5.6 Concluding Remarks 91 6 Conclusion 94 Bibliography 96 Abstract in Korean 110 감사의 글 112Docto

Study of organic molecules and nano-particle/polymer composites for flash memory and switch applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 205-218).Organic materials exhibit fascinating optical and electronic properties which motivate their hybridization with traditional silicon-based electronics in order to achieve novel functionalities and address scaling challenges of these devices. The application of organic molecules and nano-particle/polymer composites for flash memory and switch applications is studied in this dissertation. Facilitating data storage on individual small molecules as the approach the limits in miniaturization for ultra-high density and low power consumption media may enable orders of magnitude increase in data storage capabilities. A floating gate consisting of a thin film of molecules would provide the advantage of a uniform set of identical nano-structured charge storage elements with high molecular area densities which can result in a several-fold higher density of charge-storage sites as compared to quantum dot (QD) memory and even SONOS devices. Additionally, the discrete charge storage in such nano-segmented floating gate designs limits the impact of any tunnel oxide defects to the charge stored in the proximity of the defect site. The charge retention properties of molecular films was investigated in this dissertation by injecting charges via a biased conductive atomic force microscopy (AFM) tip into molecules comprising the thin films. The Kelvin force microscopy (KFM) results revealed minimal changes in the spatial extent of the charge trapping over time after initial injection. Fabricated memory capacitors show a device durability over 105 program/erase cycles and hysteresis window of up to 12.8 V, corresponding to stored charge densities as high as 5.4x 1013 cm-2, suggesting the potential use of organic molecules in high storage capacity memory cells. Also, these results demonstrate that charge storage properties of the molecular trapping layer can be engineered by rearranging molecules and their a-orbital overlaps via addition of dopant molecules. Finally, the design, fabrication, testing and evaluation of a MEMS switch that employs viscoelastic organic polymers doped with nano-particles as the active material is presented in this dissertation. The conductivity of the nano-composite changes 10,000-fold as it is mechanically compressed. In this demonstration the compressive squeeze is applied with electric actuation. Since squeezing initiates the switching behavior, the device is referred to as a "squitch". The squitch is essentially a new type of FET that is compatible with large area processing with printing or photolithography, on rigid or flexible substrates and can exhibit large on-to-off conduction ratio.by Sarah Paydavosi.Ph.D

Designs for increasing reliability while reducing energy and increasing lifetime

In the last decades, the computing technology experienced tremendous developments. For instance, transistors' feature size shrank to half at every two years as consistently from the first time Moore stated his law. Consequently, number of transistors and core count per chip doubles at each generation. Similarly, petascale systems that have the capability of processing more than one billion calculation per second have been developed. As a matter of fact, exascale systems are predicted to be available at year 2020. However, these developments in computer systems face a reliability wall. For instance, transistor feature sizes are getting so small that it becomes easier for high-energy particles to temporarily flip the state of a memory cell from 1-to-0 or 0-to-1. Also, even if we assume that fault-rate per transistor stays constant with scaling, the increase in total transistor and core count per chip will significantly increase the number of faults for future desktop and exascale systems. Moreover, circuit ageing is exacerbated due to increased manufacturing variability and thermal stresses, therefore, lifetime of processor structures are becoming shorter. On the other side, due to the limited power budget of the computer systems such that mobile devices, it is attractive to scale down the voltage. However, when the voltage level scales to beyond the safe margin especially to the ultra-low level, the error rate increases drastically. Nevertheless, new memory technologies such as NAND flashes present only limited amount of nominal lifetime, and when they exceed this lifetime, they can not guarantee storing of the data correctly leading to data retention problems. Due to these issues, reliability became a first-class design constraint for contemporary computing in addition to power and performance. Moreover, reliability even plays increasingly important role when computer systems process sensitive and life-critical information such as health records, financial information, power regulation, transportation, etc. In this thesis, we present several different reliability designs for detecting and correcting errors occurring in processor pipelines, L1 caches and non-volatile NAND flash memories due to various reasons. We design reliability solutions in order to serve three main purposes. Our first goal is to improve the reliability of computer systems by detecting and correcting random and non-predictable errors such as bit flips or ageing errors. Second, we aim to reduce the energy consumption of the computer systems by allowing them to operate reliably at ultra-low voltage level. Third, we target to increase the lifetime of new memory technologies by implementing efficient and low-cost reliability schemes

TIME-DIFFERENCE CIRCUITS: METHODOLOGY, DESIGN, AND DIGITAL REALIZATION

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: high-resolution, high-throughput, and low-design complexity with digital integration capability. Further, the fabrication technology is advancing into the nanometer regime; the reduction in voltage headroom limits the performance of traditional analog/mixed-signal designs. All-digital design of time-difference circuit needs to be stressed to adapt to the low-cost, low-power, and high-portability applications. We focus on Time-to-Digital Converters (TDC), one of the crucial building blocks in TD circuits. A novel algorithmic architecture is proposed based on a binary search algorithm and validated with both simulation and fabricated silicon. An all-digital structure Time-difference Amplifier (TDA) is designed and implemented to make FPGA and other all-digital implementations for TDC and related TD circuits feasible. Besides, we propose an all-digital timing measurement circuit based on the process variation from CMOS fabrication: PVTMC, which achieves a high measurement resolution: