Perspective of buried oxide thickness variation on triple metal-gate (TMG) recessed-S/D FD-SOI MOSFET

Recently, Fully-Depleted Silicon on Insulator (FD-SOI) MOSFETs have been accepted as a favourable technology beyond nanometer nodes, and the technique of Recessed-Source/Drain (Re-S/D) has made it more immune in regards of various performance factors. However, the proper selection of Buried-Oxide (BOX) thickness is one of the major challenges in the design of FD-SOI based MOS devices in order to suppress the drain electric penetrations across the BOX interface efficiently. In this work, the effect of BOX thickness on the performance of TMG Re-S/D FD-SOI MOSFET has been presented at 60 nm gate length. The perspective of BOX thickness variation has been analysed on the basis of its surface potential profile and the extraction of the threshold voltage by performing two-dimensional numerical simulations. Moreover, to verify the short channel immunity, the impact of gate length scaling has also been discussed. It is found that the device attains two step-up potential profile with suppressed short channel effects. The outcomes reveal that the Drain Induced Barrier Lowering (DIBL) values are lower among conventional SOI MOSFETs. The device has been designed and simulated by using 2D numerical ATLAS Silvaco TCAD simulator

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Discrimination of surface and volume states in fully depleted field-effect devices on thick insulator substrates

The behavior of electronic devices fabricated on thin, lightly doped semiconductor layers can be significantly influenced by very low levels of non-ideal charge states. Such devices typically operate in a fully depleted mode, and can exhibit significantly different electrical properties and characteristics than their bulk material counterparts. Traditional interpretation of device characteristics may identify the existence of such non-idealities, but fail to ascertain if the origin is from within the semiconductor layer or associated with the interfaces to adjacent dielectric materials. This leads to ambiguity in how to rectify the behavior and improve device performance. Characterizing non-idealities through electrical means requires adaptations in both measurement techniques and data interpretation. Some of these adaptations have been applied in material systems like silicon-on-insulator (SOI), however in systems where the semiconductor film becomes increasingly isolated on very thick insulators (i.e., glass), the device physics of operation presents new challenges. Overcoming the obstacles in interpretation can directly aid the technology development of thin semiconductor films on thick insulator substrates. The investigation is initiated by isolating the interface of crystalline silicon bonded to a thick boro-aluminosilicate glass insulator. The interface is studied through traditional bulk capacitance-voltage (C-V) methods, and the electrical fragility of the interface is exposed. This reveals the necessity to discriminate between interface states and bulk defect states. To study methods of discrimination, the physics of field-effect devices fabricated on isolated semiconducting films is explained. These devices operate in a fully depleted state; expressions that describe the C-V relationship with a single gate electrode are derived and explored. The discussion presents an explanation of how surface and volume charge states each contribute to the C-V characteristic behavior. Application of this adapted C-V theory is then applied to the gated-diode, a novel device which has proven to be instrumental in charge state discrimination. Through this adaptation, the gated-diode is used to extract recombination-generation parameters isolated to the top surface, bottom surface and within the volume of the film. The methodology is developed through an exploration of devices fabricated on SOI and silicon-on-glass (SiOG) substrates, and furthers the understanding needed to improve material quality and device performance

Reliability Investigations of MOSFETs using RF Small Signal Characterization

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliograph

Annual Report 2020 - Institute of Ion Beam Physics and Materials Research

As for everybody else also for the Institute of Ion Beam Physics and Materials Research (IIM), the COVID-19 pandemic overshadowed the usual scientific life in 2020. Starting in March, home office became the preferred working environment and the typical institute life was disrupted. After a little relaxation during summer and early fall, the situation became again more serious and in early December we had to severely restrict laboratory activities and the user operation of the Ion Beam Center (IBC). For the most part of 2020, user visits were impossible and the services delivered had to be performed hands-off. This led to a significant additional work load on the IBC staff. Thank you very much for your commitment during this difficult period. By now user operation has restarted, but we are still far from business as usual. Most lessons learnt deal with video conference systems, and everybody now has extensive experience in skype, teams, webex, zoom, or any other solution available. Conferences were cancelled, workshops postponed, and seminar or colloquia talks delivered online. Since experimental work was also impeded, maybe 2020 was a good year for writing publications and applying for external funding. In total, 204 articles have been published with an average impact factor of about 7.0, which both mark an all-time high for the Institute. 13 publications from last year are highlighted in this Annual Report to illustrate the wide scientific spectrum of our institute. In addition, 20 new projects funded by EU, DFG, BMWi/AiF and SAB with a total budget of about 5.7 M€ have started. Thank you very much for making this possible. Also, in 2020 there have been a few personalia to be reported. Prof. Dr. Sibylle Gemming has left the HZDR and accepted a professor position at TU Chemnitz. Congratulations! The hence vacant position as the head of department was taken over by PD Dr. Artur Erbe by Oct. 1st. Simultaneously, the department has been renamed to “Nanoelectronics”. Dr. Alina Deac has left the institute in order to dedicate herself to new opportunities at the Dresden High Magnetic Field Laboratory. Dr. Matthias Posselt went to retirement after 36 years at the institute. We thank Matthias for his engagement and wish him all the best for the upcoming period of his life. However, also new equipment has been setup and new laboratories founded. A new 100 kV accelerator is integrated into our low energy ion nanoengineering facility and complements our ion beam technology in the lower energy regime. This setup is particularly suited to perform ion implantation into 2D materials and medium energy ion scattering (MEIS). Finally, we would like to cordially thank all partners, friends, and organizations who supported our progress in 2020. First and foremost we thank the Executive Board of the Helmholtz-Zentrum Dresden-Rossendorf, the Minister of Science and Arts of the Free State of Saxony, and the Ministers of Education and Research, and of Economic Affairs and Energy of the Federal Government of Germany. Many partners from univer¬sities, industry and research institutes all around the world contributed essentially, and play a crucial role for the further development of the institute. Last but not least, the directors would like to thank all members of our institute for their efforts in these very special times and excellent contributions in 2020

Journal of Telecommunications and Information Technology, 2000, nr 3,4

kwartalni

Exploration of advanced CMOS technologies for new pixel detector concepts in High Energy Physics

This thesis presents the author’s original concepts for the development of radiation hard monolithic pixel sensors that can replace hybrid pixel sensors in high energy physics experiments. It presents one of the first practical implementations of monolithic pixel sensors that potentially offer performance figures similar to those of the hybrid pixel technology with fewer material and for a fraction of the cost. Various pixel sensor prototypes in different technologies have been designed and manufactured for the first time. Prototypes allowed the characterization of the basic components of active pixel sensors and the evaluation of device parameters. Presented devices show strong indications that monolithic sensors can achieve very high radiation tolerance with parameters similar to the existing hybrid technology. Other application areas like X-ray imaging may also benefit from this development

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

Physics based modeling of multiple gate transistors on Silicon-on-Insulator (SOI)

G⁴FET is a novel device built on Silicon-on-Isulator (SOI). Due to the presence of Bulk-Si, it is impossible to have more than one gate for each transistor in conventional process technology. However, it is possible to have multiple gates for each transistor in SOI devices due to the presence of buried oxide, which can be used as an independent gate. Besides the oxide gates, junction gates can also be introduced. Due to the presence of the thin active layer, the junction gate can reach to the bottom and can be used to isolate and control the conduction in the transistors. As a result, the maximum number of gates that can be achieved in SOI is four. A transistor with four gates is called G⁴FET. G⁴FET offers all the features of SOI technology. It offers remedies of the drawbacks of Bulk-Si technology. The operation of the multiple gates has applications for mixed-signal circuits, quantum wire, and single transistor multiple gates logic schemes, etc. The research goal is to understand the device physics of G⁴FET. Understanding device physics will provide enough information to set device parameters to optimize device performances. The operation of semiconductor devices depends on several material parameters, device dimensions and structure. The objective of this research is to develop a model that includes material parameters, device dimensions and structure. The second objective of this research is to develop a numerical model from available data. The numerical model is useful for circuit simulation of G⁴FET, which provides information about the characteristics of G⁴FET, when used as a circuit element