Degradation in FPGAs: Monitoring, Modeling and Mitigation

This dissertation targets the transistor aging degradation as well as the associated thermal challenges in FPGAs (since there is an exponential relation between aging and chip temperature). The main objectives are to perform experimentation, analysis and device-level model abstraction for modeling the degradation in FPGAs, then to monitor the FPGA to keep track of aging rates and ultimately to propose an aging-aware FPGA design flow to mitigate the aging

Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation

The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship’s integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation

An FPGA Noise Resistant Digital Temperature Sensor with Auto Calibration

In recent years, thermal sensing in digital devices has become increasingly important. From a security perspective, new thermal-based attacks have revealed vulnerabilities in digital devices. Traditional temperature sensors using analog-to-digital converters consume significant power and are not conducive to rapid development. As a result, there has been an escalating demand for low cost, low power digital temperature sensors that can be seamlessly integrated onto digital devices. This research seeks to create a modular Field Programmable Gate Array digital temperature sensor with auto one-point calibration to eliminate the excessive costs and time associated with calibrating existing digital temperature sensors. In addition, to support the auxiliary protection role, the sensor is evaluated alongside a RSA circuit implemented on the same chip, with methods developed to mitigate noise and power fluctuations introduced by the main circuit. The result is a digital temperature sensor resistant to noise and suitable for quick mass deployment in digital devices

Mitigating impacts of workload variation on ring oscillator-based thermometers.

Thermal issues have resulted in growing concerns among industries fabricating semiconductor devices such as Chip Multiprocessors (CMP) and reconfigurable hardware devices. To reduce passive cooling costs and eliminate the need to package for worst-case temperatures, dynamic thermal management (DTM) techniques are being devised to combat thermal effects. Reliable runtime measurement of device temperature is necessary for implementing DTM techniques. Ring oscillators have often been used for on-chip Field Programmable Gate Array (FPGA) temperature measurement due to their strong linear temperature dependence and compact design using available spare reconfigurable resources. A major problem in using ring oscillators to measure temperature, however, is that their frequency of oscillation is affected by changes in device core voltage and current distribution, induced by changes in application workload. The need, then, is to have a workload-compensated ring oscillator-based thermometer for reconfigurable devices. This work performs a characterization of the ideal as well as non-ideal effects of workload variation on ring oscillator frequency response. Where non-ideal refers to impacts on ring oscillator oscillation frequency due to phenomena other than the workload\u27s impact on device temperature. The data obtained from this characterization is used to compensate for these non-ideal effects. A complete hardware-software solution is implemented to collect temperature and power related data along with ring oscillator frequency response to varying workload configurations. The characterization results show an error of approximately 1°C in the estimated temperature for every 8.6mA change in current drawn from the supply on a Xilinx Virtex-5 LX110T FPGA, with respect to the current draw measured while running a baseline workload during thermometer calibration. This lead to a maximum error of ∼74°C for the workloads evaluated. The compensation technique implemented is shown to reduce this error to ∼2°C. In addition, a potential issue with using the Xilinx System Monitor to measure die temperature at high temperatures is observed. The System Monitor reported temperatures show a deviation of up to 20°C from temperatures obtained using a case-mounted thermal probe

Thermal monitoring on FPGAs using ring-oscillators

The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-63465-7_212Proceedings of 7th International Workshop, FPL '97 London, UK, September 1–3, 1997In this paper, a temperature-to-frequency transducer suitable for thermal monitoring on FPGAs is presented. The dependence between delay and temperature is used to produce a frequency drift on a ring-oscillator. Different sensors have been constructed and characterized using XC4000 and XC3000 chips, obtaining typical sensibilities of 50 kHz per °C. In addition, the utility of the Xilinx OSC4 cell as thermal transducer has been demonstrated. Although a complete temperature verification system requires a control unit with a frequency counter, the use of ring-oscillators presents several advantages: minimum FPGA elements are required; no analog parts exists; the additional hardware needed (multiplexers, prescaler, etc.) can be constructed using the resources of an FPGA, the thermal-related signals can be routed employing the standard interconnection network of the board, and finally, the sensors can be dynamically inserted or eliminated.This work has been supported by the CICYT of Spain under contract TIC95-0159. The authors wish to thank Javier Garrido for his valuable contribution during the setup of the experiments

FlashCam: a fully-digital camera for the medium-sized telescopes of the Cherenkov Telescope Array

The FlashCam group is currently preparing photomultiplier-tube based cameras proposed for the medium-sized telescopes (MST) of the Cherenkov Telescope Array (CTA). The cameras are designed around the FlashCam readout concept which is the first fully-digital readout system for Cherenkov cameras, based on commercial FADCs and FPGAs as key components for the front-end electronics modules and a high performance camera server as back-end. This contribution describes the progress of the full-scale FlashCam camera prototype currently under construction, as well as performance results also obtained with earlier demonstrator setups. Plans towards the production and implementation of FlashCams on site are also briefly presented.Comment: 8 pages, 6 figures. In Proceedings of the 34th International Cosmic Ray Conference (ICRC2015), The Hague, The Netherlands. All CTA contributions at arXiv:1508.0589

Pre-Flight Testing and Performance of a Ka-Band Software Defined Radio

National Aeronautics and Space Administration (NASA) has developed a space-qualified, reprogrammable, Ka-band Software Defined Radio (SDR) to be utilized as part of an on-orbit, reconfigurable testbed. The testbed will operate on the truss of the International Space Station beginning in late 2012. Three unique SDRs comprise the testbed, and each radio is compliant to the Space Telecommunications Radio System (STRS) Architecture Standard. The testbed provides NASA, industry, other Government agencies, and academic partners the opportunity to develop communications, navigation, and networking applications in the laboratory and space environment, while at the same time advancing SDR technology, reducing risk, and enabling future mission capability. Designed and built by Harris Corporation, the Ka-band SDR is NASA's first space-qualified Ka-band SDR transceiver. The Harris SDR will also mark the first NASA user of the Ka-band capabilities of the Tracking Data and Relay Satellite System (TDRSS) for on-orbit operations. This paper describes the testbed's Ka-band System, including the SDR, travelling wave tube amplifier (TWTA), and antenna system. The reconfigurable aspects of the system enabled by SDR technology are discussed and the Ka-band system performance is presented as measured during extensive pre-flight testing

Spectrometer Scan Mechanism for Encountering Jovian Orbit Trojan Asteroids

This paper describes the design, testing, and lessons learned during the development of the Lucy Ralph (L'Ralph) Scan Mirror System (SMS), composed of the Scan Mirror Mechanism (SMM), Differential Position Sensor System (DPSS) and Mechanism Control Electronics (MCE). The L'Ralph SMS evolved from the Advanced Topographic Laser Altimeter System (ATLAS) Beam Steering Mechanism (BSM), so design comparisons will be made. Lucy is scheduled to launch in October 2021, embarking upon a 12-year mission to make close range encounters in 2025 and 2033 with seven Trojan asteroids and one main belt asteroid that are within the Jovian orbit. The L'Ralph instrument is based upon the New Horizons Ralph instrument, which is a panchromatic and color visible imager and infrared spectroscopic mapper that slewed the spacecraft for imaging. The L'Ralph SMM is to provide scanning for imaging to eliminate the need to slew the spacecraft. One purpose of this paper is to gain understanding of the reasoning behind some of the design features as compared with the ATLAS BSM. We will identify similarities and differences between the ATLAS BSM and the L'Ralph SMM that resulted from the latter's unique requirements. Another purpose of this paper is to focus upon "Lessons Learned" that came about during the development of the L'Ralph SMM and its MCE, both mechanism engineering issues and solutions as well as Ground Support Equipment (GSE) issues and solutions that came about during the validation of requirements process. At the time of this writing, the L'Ralph SMM has been flight qualified and delivered to the project

DEVELOPMENT, INTEGRATION, AND EVALUATION OF LIGHTWEIGHT MATERIALS FOR CUBESAT ARCHITECTURES​

Reductions in size, weight, and power requirements have been continuously sought for space systems. With small satellite technology continuing to leverage the miniaturization of electronics, pushing the boundaries of size and weight is a synergistic effort that enables the development of national capabilities in space. Currently, small satellite technology is often limited by the temperature limits of certain components, such as processors and batteries, and the high costs of placing them in orbit. The effort described herein is the additive manufacturing approach pursued to develop, fabricate, and integrate lightweight materials on a CubeSat. The hypothesis was that commercial filaments could be used to 3D print a radio housing that would have sufficient electrical, mechanical, and thermal properties to replace the original 6061 aluminum alloy. Some of the materials tested included carbon nanotube epoxy composites, carbon fiber reinforced nylon, carbon fiber reinforced polyethylene terephthalate-glycol, polycaprolactone infused with copper, and combinations of the filaments. Diverse radio housing samples were fabricated, integrated, and tested. Additively manufactured parts resulted in acceptable, RF shielding and mechanical and thermal conductivity values. Additionally, there was an 86% savings for cost and 80% less weight than the original aluminum alloy, proving the potential that other material and manufacturing approaches could have in developing CubeSats.DoD Space , Chantilly, VALieutenant Commander, United States NavyApproved for public release. Distribution is unlimited