Enhanced low bitrate H.264 video coding using decoder-side super-resolution and frame interpolation

Advanced inter-prediction modes are introduced recently in literature to improve video coding performances of both H.264 and High Efficiency Video Coding standards. Decoder-side motion analysis and motion vector derivation are proposed to reduce coding costs of motion information. Here, we introduce enhanced skip and direct modes for H.264 coding using decoder-side super-resolution (SR) and frame interpolation. P-and B-frames are downsampled and H.264 encoded at lower resolution (LR). Then reconstructed LR frames are super-resolved using decoder-side motion estimation. Alternatively for B-frames, bidirectional true motion estimation is performed to synthesize a B-frame from its reference frames. For P-frames, bicubic interpolation of the LR frame is used as an alternative to SR reconstruction. A rate-distortion optimal mode selection algorithm is developed to decide for each MB which of the two reconstructions to use as skip/direct mode prediction. Simulations indicate an average of 1.04 dB peak signal-to-noise ratio (PSNR) improvement or 23.0% bitrate reduction at low bitrates when compared with H.264 standard. The PSNR gains reach as high as 3.00 dB for inter-predicted frames and 3.78 dB when only B-frames are considered. Decoded videos exhibit significantly better visual quality as well.This research was supported by TUBITAK Career Grant 108E201Publisher's Versio

Data compression systems for home-use digital video recording

The authors focus on image data compression techniques for digital recording. Image coding for storage equipment covers a large variety of systems because the applications differ considerably in nature. Video coding systems suitable for digital TV and HDTV recording and digital electronic still picture storage are considered. In addition, attention is paid to picture coding for interactive systems, such as the compact-disc interactive system. The relation between the recording system boundary conditions and the applied coding techniques is outlined. The main emphasis is on picture coding techniques for digital consumer recordin

Row Compression and Nested Product Decomposition of a Hierarchical Representation of a Quasiseparable Matrix

This research introduces a row compression and nested product decomposition of an nxn hierarchical representation of a rank structured matrix A, which extends the compression and nested product decomposition of a quasiseparable matrix. The hierarchical parameter extraction algorithm of a quasiseparable matrix is efficient, requiring only O(nlog(n))operations, and is proven backward stable. The row compression is comprised of a sequence of small Householder transformations that are formed from the low-rank, lower triangular, off-diagonal blocks of the hierarchical representation. The row compression forms a factorization of matrix A, where A = QC, Q is the product of the Householder transformations, and C preserves the low-rank structure in both the lower and upper triangular parts of matrix A. The nested product decomposition is accomplished by applying a sequence of orthogonal transformations to the low-rank, upper triangular, off-diagonal blocks of the compressed matrix C. Both the compression and decomposition algorithms are stable, and require O(nlog(n)) operations. At this point, the matrix-vector product and solver algorithms are the only ones fully proven to be backward stable for quasiseparable matrices. By combining the fast matrix-vector product and system solver, linear systems involving the hierarchical representation to nested product decomposition are directly solved with linear complexity and unconditional stability. Applications in image deblurring and compression, that capitalize on the concepts from the row compression and nested product decomposition algorithms, will be shown

Low power data-dependent transform video and still image coding

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Includes bibliographical references (p. 139-144).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.This work introduces the idea of data dependent video coding for low power. Algorithms for the Discrete Cosine Transform (DCT) and its inverse are introduced which exploit statistical properties of the input data in both the space and spatial frequency domains in order to minimize the total number of arithmetic operations. Two VLSI chips have been built as a proof-of-concept of data dependent processing implementing the DCT and its inverse (IDCT). The IDCT core processor exploits the presence of a large number of zerovalued spectral coefficients in the input stream when stimulated with MPEG-compressed video sequences. Adata-driven IDCT computation algorithm along with clock gating techniques are used to reduce the number of arithmetic operations for video inputs. The second chip is a DCT core processor that exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context along with standard voltage scaling techniques such as pipelining and parallelism. The first method reduces the bitwidth of arithmetic operations in the presence of data spatial correlation. The second method trades off power dissipation and image compression quality (arithmetic precision.) Both chips are fully functional and exhibit the lowest switched capacitance per sample among past DCT/IDCT chips reported in the literature. Their power dissipation profile shows a strong dependence with certain statistical properties of the data that they operate on, according to the design goal.by Thucydides Xanthopoulos.Ph.D

Stereoscopic video coding.

by Roland Siu-kwong Ip.Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.Includes bibliographical references (leaves 101-[105]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Image Compression --- p.2Chapter 1.2.1 --- Classification of Image Compression --- p.2Chapter 1.2.2 --- Lossy Compression Approaches --- p.3Chapter 1.3 --- Video Compression --- p.4Chapter 1.3.1 --- Video Compression System --- p.5Chapter 1.4 --- Stereoscopic Video Compression --- p.6Chapter 1.5 --- Organization of the thesis --- p.6Chapter 2 --- Motion Video Coding Theory --- p.8Chapter 2.1 --- Introduction --- p.8Chapter 2.2 --- Representations --- p.8Chapter 2.2.1 --- Temporal Processing --- p.13Chapter 2.2.2 --- Spatial Processing --- p.19Chapter 2.3 --- Quantization --- p.25Chapter 2.3.1 --- Scalar Quantization --- p.25Chapter 2.3.2 --- Vector Quantization --- p.27Chapter 2.4 --- Code Word Assignment --- p.29Chapter 2.5 --- Selection of Video Coding Standard --- p.31Chapter 3 --- MPEG Compatible Stereoscopic Coding --- p.34Chapter 3.1 --- Introduction --- p.34Chapter 3.2 --- MPEG Compatibility --- p.36Chapter 3.3 --- Stereoscopic Video Coding --- p.37Chapter 3.3.1 --- Coding by Stereoscopic Differences --- p.37Chapter 3.3.2 --- I-pictures only Disparity Coding --- p.40Chapter 3.4 --- Stereoscopic MPEG Encoder --- p.44Chapter 3.4.1 --- Stereo Disparity Estimator --- p.45Chapter 3.4.2 --- Improved Disparity Estimation --- p.47Chapter 3.4.3 --- Stereo Bitstream Multiplexer --- p.49Chapter 3.5 --- Generic Implementation --- p.50Chapter 3.5.1 --- Macroblock Converter --- p.54Chapter 3.5.2 --- DCT Functional Block --- p.55Chapter 3.5.3 --- Rate Control --- p.57Chapter 3.6 --- Stereoscopic MPEG Decoder --- p.58Chapter 3.6.1 --- Mono Playback --- p.58Chapter 3.6.2 --- Stereo Playback --- p.60Chapter 4 --- Performance Evaluation --- p.63Chapter 4.1 --- Introduction --- p.63Chapter 4.2 --- Test Sequences Generation --- p.63Chapter 4.3 --- Simulation Environment --- p.64Chapter 4.4 --- Simulation Results --- p.65Chapter 4.4.1 --- Objective Results --- p.65Chapter 4.4.2 --- Subjective Results --- p.72Chapter 5 --- Conclusions --- p.80Chapter A --- MPEG ´ؤ An International Standard --- p.83Chapter A.l --- Introduction --- p.83Chapter A.2 --- Preprocessing --- p.84Chapter A.3 --- Data Structure of Pictures --- p.85Chapter A.4 --- Picture Coding --- p.86Chapter A.4.1 --- Coding of Motion Vectors --- p.90Chapter A.4.2 --- Coding of Quantized Coefficients --- p.94References --- p.10

Discrete Wavelet Transforms

The discrete wavelet transform (DWT) algorithms have a firm position in processing of signals in several areas of research and industry. As DWT provides both octave-scale frequency and spatial timing of the analyzed signal, it is constantly used to solve and treat more and more advanced problems. The present book: Discrete Wavelet Transforms: Algorithms and Applications reviews the recent progress in discrete wavelet transform algorithms and applications. The book covers a wide range of methods (e.g. lifting, shift invariance, multi-scale analysis) for constructing DWTs. The book chapters are organized into four major parts. Part I describes the progress in hardware implementations of the DWT algorithms. Applications include multitone modulation for ADSL and equalization techniques, a scalable architecture for FPGA-implementation, lifting based algorithm for VLSI implementation, comparison between DWT and FFT based OFDM and modified SPIHT codec. Part II addresses image processing algorithms such as multiresolution approach for edge detection, low bit rate image compression, low complexity implementation of CQF wavelets and compression of multi-component images. Part III focuses watermaking DWT algorithms. Finally, Part IV describes shift invariant DWTs, DC lossless property, DWT based analysis and estimation of colored noise and an application of the wavelet Galerkin method. The chapters of the present book consist of both tutorial and highly advanced material. Therefore, the book is intended to be a reference text for graduate students and researchers to obtain state-of-the-art knowledge on specific applications

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design