Reliability Analysis of Power Electronic Devices

The thesis deals with the reliability of Power Electronic Devices to the purpose of evaluating the phenomena which mainly dictate the limiting conditions where a power device can safely operate. Reliability analyses are conducted by means of either simulations and experimental measurements

Finite element electrothermal modelling and characterization of single and parallel connected power devices

Power modules typically comprise of several power devices connected in parallel for the purpose of delivering high current capability. This is especially the case in SiC where small active area and low current MOSFETs are the only option due to defect density control and yield issues in the epitaxial growth of SiC wafers. Electrothermal variations between parallel connected devices can emerge from manufacturing variability, non-uniform degradation rates, variation in gate driving just to mention a few. The impact of electrothermal variation between parallel-connected devices as a function of device technology is thus important to consider especially since failure of the power module requires only failure in a single device. Furthermore, the impact of these electrothermal variations in parallel-connected devices on the total electrothermal ruggedness of the power module under anomalous switching conditions like unclamped inductive switching is important to consider for the different device technologies. In this thesis, the impact of initial junction temperature variation, switching rates and thermal boundary conditions between parallel-connected diodes have been evaluated for SiC Schottky and silicon PiN diodes under clamped and unclamped inductive switching. Finite element simulations have been used to support the experimental measurements. Similar studies have been performed in CoolMOS super-junction MOSFETs, silicon IGBTs and SiC power MOSFETs. New insights regarding the failure of parallel connected devices under unclamped inductive switching have been revealed from the models and measurements. Overall, the thesis makes a major contribution in the understanding of the electrothermal performance of parallel connected devices for different transistor and diode technologies

Design and Control of Power Converters 2020

In this book, nine papers focusing on different fields of power electronics are gathered, all of which are in line with the present trends in research and industry. Given the generality of the Special Issue, the covered topics range from electrothermal models and losses models in semiconductors and magnetics to converters used in high-power applications. In this last case, the papers address specific problems such as the distortion due to zero-current detection or fault investigation using the fast Fourier transform, all being focused on analyzing the topologies of high-power high-density applications, such as the dual active bridge or the H-bridge multilevel inverter. All the papers provide enough insight in the analyzed issues to be used as the starting point of any research. Experimental or simulation results are presented to validate and help with the understanding of the proposed ideas. To summarize, this book will help the reader to solve specific problems in industrial equipment or to increase their knowledge in specific fields

Electrothermal Modelling for Doubly Fed Induction Generator Converter Reliability in Wind Power

Increased reliance upon renewable energy sources, chiefly wind, places a growing emphasis on the reliability of the technology used in Wind Turbines. The current Wind Turbine fleet is dominated by the Doubly Fed Induction Machine WT, which utilises a partially rated power electronic converter to vary the speed of the rotor and thus ensure the maximum energy capture available from the wind. This converter is associated with a significant percentage of WT failures. This thesis examines the low frequency temperature cycling occurring in one half of the back to back converter which results in a high failure rate of the rotor side converter as compared to the grid side converter. To this end a MATLAB/PLECS model was constructed to demonstrate the temperature cycling occurring in a 2.5MW DFIG WT. Lifetime of the semiconductor devices was extrapolated. An adaptation to the standard Maximum Power Point Tracking control method was suggested in which the lowest operating frequencies (less than 2.33Hz) were avoided. In doing so, lifetime was observed to increase at a minor cost to energy yield from the WT

Characterization and evaluation of a 6.5-kV silicon carbide bipolar diode module

This work presents a 6.5-kV 1-kA SiC bipolar diode module for megawatt-range medium voltage converters. The study comprises a review of SiC devices and bipolar diodes, a description of the die and module technology, device characterization and modelling and benchmark of the device at converter level. The effects of current change rate, temperature variation, and different insulated-gate bipolar transistor (IGBT) modules for the switching cell, as well as parasitic oscillations are discussed. A comparison of the results with a commercial Si diode (6.5 kV and 1.2 kA) is included. The benchmark consists of an estimation of maximum converter output power, maximum switching frequency, losses and efficiency in a three level (3L) neutral point clamped (NPC) voltage-source converter (VSC) operating with SiC and Si diodes. The use of a model predictive control (MPC) algorithm to achieve higher efficiency levels is also discussed. The analysed diode module exhibits a very good performance regarding switching loss reduction, which allows an increase of at least 10 % in the output power of a 6-MVA converter. Alternatively, the switching frequency can be increased by 41 %.:1 Introduction 2 State of the art of SiC devices and medium-voltage diodes 2.1 Silicon carbide diodes and medium-voltage modules 2.2 Medium-voltage power diodes 3 Characterization of the SiC PiN diode module 37 3.1 Introduction 3.2 Experimental setup 3.3 Experimental results: static behaviour 3.4 Experimental results: switching behaviour 3.5 Comparison with 6.5-kV silicon diode 3.6 Oscillations in the SiC diode 3.7 Summary 4 Comparison at converter level 4.1 Introduction 4.2 Power device modelling 4.3 Determination of maximum converter power rating 4.4 Analysis 4.5 Increased efficiency through model predictive control 4.6 Summary 5 Conclusio

Frequency domain temperature model :a new method in on-line temperature estimation for power modules in drives applications

D. Eng.The operating temperature of the components within an electronic device has a significant impact on the reliability of a product. In a variable speed drive the power semiconductors in the inverter stage are often operated close to their maximum temperature when the inverter is operating at a low output frequency or during an overload. The temperature of these components must be continuously monitored to prevent them from overheating, but direct measurement of the temperature is only possible if a special test configuration can be used. This is not practicable in a commercial drive and to protect the inverter the temperature of the power semiconductors must be estimated by an on-line thermal model. The work presented in this thesis describes the development of a novel thermal model that can be implemented using the existing computational resources available in a commercial variable speed drive. The thermal model is based on the transient thermal impedance measured between each device and the internal thermistor in a power module. These form a thermal impedance matrix which can be used to calculate the instantaneous temperature of every device in the inverter. However, with the existing computational resources it is not possible to implement the complete matrix without aliasing. To reduce the risk of aliasing the number of calculations performed during each sample period must be reduced. This is achieved by using a frequency domain model that has been developed to calculate the peak temperature of the hottest devices. To validate the thermal model it has been implemented in a commercial drive. The drive has been modified to allow the temperature of the power semiconductors in the inverter to be measured using a high speed thermal camera. This allows the temperature estimated by the on-line thermal model to be compared directly with the temperatures measured when the inverter is operating under typical load conditions. Comparisons of the measured and estimated temperatures in several operating conditions are presented. These conditions were chosen to highlight the advantages and disadvantages of the frequency domain model

Optimisation of High Reliability Integrated Motor Drives

The development of integrated motor drives (IMDs) with high volumetric power density and reliability are crucial for the continued development and adoption of electric vehicles (EV). The development of the wide bandgap (WBG) devices, especially Silicon Carbide (SiC) MOSFETs, enables new possibilities for traction drive systems. However, to maximise the benefits of SiC, the IMD design process, including passive component selection, control and thermal management should be optimised. This thesis goes through the initial major design steps in SiC power system design, from SiC device analysis and modelling to circuit design and electrothermal simulation of an IMD system. A novel approach to discrete SiC MOSFET selection, using a method of calculating performance based on experimental data, is described. Dynamic behaviour of a family of 1200 V MOSFETs is studied at temperatures up to 175 °C using a double pulse test to show the combined effect of the differences in internal design between MOSFETs with different current ratings. It is observed that the 30 mΩ MOSFET had a 24 % higher switching loss than a 140 mΩ at a 30 A load current. The study then goes on to compare the effect of switching frequency, paralleling of MOSFETs and the device type used to demonstrate the inverter design with the lowest power losses, which will equate to low temperatures and high lifetime. The novel methodology can find the optimal choice of MOSFET from the family, and number required through paralleling, for a circuit when given the load current, temperature and switching. Understanding the device interdependencies in a single family is utilised to also predict the relative performance between SiC MOSFETs from different manufacturers. An axial-flux permanent magnet synchronous motor (PMSM) driven by a three-phase SiC inverter is simulated in PLECS using experimentally validated MOSFET models chosen by the device selection methodology. Electrothermal analysis shows the influence of switching frequency, temperature, MOSFETs paralleling and DC-link capacitance on voltage ripple, total harmonic distortion, efficiency and MOSFET loss and temperature profiles. With a 60 % decrease in THD and 50 % increase in maximum MOSFET junction temperature when switching frequency is increased from 10 to 100 kHz. The high-temperature stress on the semiconductors due to close proximity with the ma- chine stator means reliability is an important consideration that is yet to be fully investigated in IMD optimisations. This study uses a lifetime model specific to the transistor package TO-247 in reliability optimisation for IMD for the first time. It requires detailed MOSFET simulation outputs to provide a highly accurate lifetime for discrete SiC MOSFETs. Both single and multi-objective optimisations of the volume and lifetime of the three- phase inverter are presented. The single objective optimisation demonstrates the minimum volume and the corresponding switching frequency and lifetime when between three and six MOSFETs are paralleled at a temperature range between 50 and 150 °C. Design constraints were set limiting the feasible switching frequency range to between 13 kHz because of THD and 118 kHz because of efficiency limits, corresponding to required DC-link capacitors of 520 and 55 μF respectively. Increases in temperature were found to further limit the maximum switching frequency and therefore increase the minimum volume of the inverter. A Pareto front identifies a range of possible solutions for the volume and lifetime of an inverter with six paralleled MOSFETs through the multi-objective objective procedure. Further analysis of these possible solutions identified a single optimal solution for the system, using a DC-link capacitance of 190 μF at 45 kHz, giving a combined volume of the capacitor and MOSFETs of 440 cm3 and a lifetime of 12,000 hours. Finally, the electrothermal analysis of a dual inverter driving a symmetric six-phase PMSM is presented with the benefits of modular multi-phase systems in IMDs summarised. Effect on performance of lower per-phase current, interleaving strategies and fault tolerance are analysed and compared to equivalent three-phase systems, for 60 kW and 120 kW operation. A novel method for lifetime prediction of systems with paralleled MOSFETs or fault tolerance capabilities considering incremental damage is developed based on TO-247 lifetime calculations from PLECS simulation, and component-level reliability profiles using Monte Carlo analysis. The dual inverter is used to model the system and implements control schemes for both single-phase and single inverter failure while maintaining the 4000 rpm and 140 Nm speed and torque requirements. A twofold increase in B10 lifetime of is observed when the effect of paralleled SiC MOSFETs prevents immediate system failure in a three-phase inverter. A computational fluid dynamics (CFD) and 3D finite element thermal model are designed to study the inverter behaviour based on the thermal analysis of its shared cooling plate with a 300 mm diameter axial flux PMSM. Concentric layout designs minimise the variation of junction temperatures to 5 °C and the effect of the flow rate and temperature of the coolant in the PMSM cold plate is presented between 5 and 30 l/min. The multi-objective optimisation procedure used to compare the dual inverter demonstrated it outperformed the three-phase inverter with 15 % smaller required DC-link capacitance, higher efficiency and increased lifetime in part due to its fault-tolerant nature. The optimal dual inverter considering the design constraints consists of four 40 μF KEMET film capacitors operating with a switching frequency of 46 kHz giving an inverter volume of 300 cm3 and a lifetime of 16.3 years, assuming 1000 hours of operation annually

Benchmarking the robustness performance of SiC cascode JFETS against contemporary devices using simulations and experimental measurements

This thesis provides the first comprehensive benchmarking exercise of SiC Cascode JFETs against similarly rated SiC Planar MOSFETs, Trench MOSFETs and other devices. Experimental measurements of short circuits in single and parallel devices, single and repetitive unclamped inductive switching as well as double pulse tests are used together with finite element simulations throughout the thesis. Power device robustness measures how well a device can sustain shocks during anomalous operation. These operating conditions are high voltages that exceed the device breakdown (avalanche conduction), or simultaneous high current and voltage through the device (Short circuit conduction). The silicon Carbide (SiC) cascode JFET is an electronic switch that combines two power devices, a low voltage silicon (Si) MOSFET and a high voltage SiC JFET operating as a single switch. This configuration avoids the challenges of reduced gate oxide reliability in SiC MOSFETs, and negative turn-on Voltage for JFETs. However, the robustness of SiC cascode JFETs have not been examined as extensively as conventional devices. Hence, this thesis investigates the robustness of SiC cascode JFETs as well as the failure modes during such operation and benchmarks the performance against conventional devices. Analysis of avalanche robustness in SiC Cascode JFETs indicated a peculiar style of failure at high temperatures characterised by a soft failure (delayed turn-off, change of current slope, and dip in voltage), and an eventual catastrophic failure. This failure is different from other devices analysed which demonstrated a single catastrophic failure. The results show that the gate resistance of the SiC JFET plays a crucial role during avalanche mode conduction. Finite element simulations confirm this observation. The Short circuit (SC) robustness analysis of the SiC Cascode JFET demonstrated invariability with temperature. In contrast, benchmarked devices show a SC correlation with temperature. The short circuit operation also revealed the Cascode JFET fails with a drain source short while the gate-source junction is still functional. Also revealed is the crucial role of increasing JFET gate resistance in reducing short circuit robustness. The SC robustness is also analysed for parallel connected devices. The analysis demonstrates the parameters with the largest impact on SC current shared between paralleled devices. Variation in the embedded JFET gate resistance within the cascode JFET presents with the highest impact as confirmed by finite element simulation, while interface charges and the doping of the CSL region present with the largest impact in SiC MOSFET

Novel Power Electronic Device Structures for Power Conditioning Applications

The work presented in this thesis contains an investigation into the methods by which the semiconductor device performance can be improved with an aim to reduce the overall losses in the power conversion system. The types of devices discussed and evaluated in this thesis include Silicon MOSFETs, IGBT, CIGBT and GaN HEMT devices. The performance improvement methods suggested in literature usually involve a trade-off of device characteristics with one another. Therefore an investigation into new device technologies and structures is deemed necessary such that the performance trade-off can be avoided or be improved