A Digital Predistortion Scheme Exploiting Degrees-of-Freedom for Massive MIMO Systems

The primary source of nonlinear distortion in wireless transmitters is the power amplifier (PA). Conventional digital predistortion (DPD) schemes use high-order polynomials to accurately approximate and compensate for the nonlinearity of the PA. This is not practical for scaling to tens or hundreds of PAs in massive multiple-input multiple-output (MIMO) systems. There is more than one candidate precoding matrix in a massive MIMO system because of the excess degrees-of-freedom (DoFs), and each precoding matrix requires a different DPD polynomial order to compensate for the PA nonlinearity. This paper proposes a low-order DPD method achieved by exploiting massive DoFs of next-generation front ends. We propose a novel indirect learning structure which adapts the channel and PA distortion iteratively by cascading adaptive zero forcing precoding and DPD. Our solution uses a 3rd order polynomial to achieve the same performance as the conventional DPD using an 11th order polynomial for a 100x10 massive MIMO configuration. Experimental results show a 70% reduction in computational complexity, enabling ultra-low latency communications.Comment: IEEE International Conference on Communications 201

Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors’ knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.Peer Reviewe

Low-Complexity Sub-band Digital Predistortion for Spurious Emission Suppression in Noncontiguous Spectrum Access

Noncontiguous transmission schemes combined with high power-efficiency requirements pose big challenges for radio transmitter and power amplifier (PA) design and implementation. Due to the nonlinear nature of the PA, severe unwanted emissions can occur, which can potentially interfere with neighboring channel signals or even desensitize the own receiver in frequency division duplexing (FDD) transceivers. In this article, to suppress such unwanted emissions, a low-complexity sub-band DPD solution, specifically tailored for spectrally noncontiguous transmission schemes in low-cost devices, is proposed. The proposed technique aims at mitigating only the selected spurious intermodulation distortion components at the PA output, hence allowing for substantially reduced processing complexity compared to classical linearization solutions. Furthermore, novel decorrelation based parameter learning solutions are also proposed and formulated, which offer reduced computing complexity in parameter estimation as well as the ability to track time-varying features adaptively. Comprehensive simulation and RF measurement results are provided, using a commercial LTE-Advanced mobile PA, to evaluate and validate the effectiveness of the proposed solution in real world scenarios. The obtained results demonstrate that highly efficient spurious component suppression can be obtained using the proposed solutions

ワイヤレス通信のための先進的な信号処理技術を用いた非線形補償法の研究

The inherit nonlinearity in analogue front-ends of transmitters and receivers have had primary impact on the overall performance of the wireless communication systems, as it gives arise of substantial distortion when transmitting and processing signals with such circuits. Therefore, the nonlinear compensation (linearization) techniques become essential to suppress the distortion to an acceptable extent in order to ensure sufficient low bit error rate. Furthermore, the increasing demands on higher data rate and ubiquitous interoperability between various multi-coverage protocols are two of the most important features of the contemporary communication system. The former demand pushes the communication system to use wider bandwidth and the latter one brings up severe coexistence problems. Having fully considered the problems raised above, the work in this Ph.D. thesis carries out extensive researches on the nonlinear compensations utilizing advanced digital signal processing techniques. The motivation behind this is to push more processing tasks to the digital domain, as it can potentially cut down the bill of materials (BOM) costs paid for the off-chip devices and reduce practical implementation difficulties. The work here is carried out using three approaches: numerical analysis & computer simulations; experimental tests using commercial instruments; actual implementation with FPGA. The primary contributions for this thesis are summarized as the following three points: 1) An adaptive digital predistortion (DPD) with fast convergence rate and low complexity for multi-carrier GSM system is presented. Albeit a legacy system, the GSM, however, has a very strict requirement on the out-of-band emission, thus it represents a much more difficult hurdle for DPD application. It is successfully implemented in an FPGA without using any other auxiliary processor. A simplified multiplier-free NLMS algorithm, especially suitable for FPGA implementation, for fast adapting the LUT is proposed. Many design methodologies and practical implementation issues are discussed in details. Experimental results have shown that the DPD performed robustly when it is involved in the multichannel transmitter. 2) The next generation system (5G) will unquestionably use wider bandwidth to support higher throughput, which poses stringent needs for using high-speed data converters. Herein the analog-to-digital converter (ADC) tends to be the most expensive single device in the whole transmitter/receiver systems. Therefore, conventional DPD utilizing high-speed ADC becomes unaffordable, especially for small base stations (micro, pico and femto). A digital predistortion technique utilizing spectral extrapolation is proposed in this thesis, wherein with band-limited feedback signal, the requirement on ADC speed can be significantly released. Experimental results have validated the feasibility of the proposed technique for coping with band-limited feedback signal. It has been shown that adequate linearization performance can be achieved even if the acquisition bandwidth is less than the original signal bandwidth. The experimental results obtained by using LTE-Advanced signal of 320 MHz bandwidth are quite satisfactory, and to the authors’ knowledge, this is the first high-performance wideband DPD ever been reported. 3) To address the predicament that mobile operators do not have enough contiguous usable bandwidth, carrier aggregation (CA) technique is developed and imported into 4G LTE-Advanced. This pushes the utilization of concurrent dual-band transmitter/receiver, which reduces the hardware expense by using a single front-end. Compensation techniques for the respective concurrent dual-band transmitter and receiver front-ends are proposed to combat the inter-band modulation distortion, and simultaneously reduce the distortion for the both lower-side band and upper-side band signals.電気通信大学201

A fast engineering approach to high efficiency power amplifier linearization for avionics applications

This PhD thesis provides a fast engineering approach to the design of digital predistortion (DPD) linearizers from several perspectives: i) enhancing the off-line training performance of open-loop DPD, ii) providing robustness and reducing the computational complexity of the parameters identification subsystem and, iii) importing machine learning techniques to favor the automatic tuning of power amplifiers (PAs) and DPD linearizers with several free-parameters to maximize power efficiency while meeting the linearity specifications. One of the essential parts of unmanned aerial vehicles (UAV) is the avionics, being the radio control one of the earliest avionics present in the UAV. Unlike the control signal, for transferring user data (such as images, video, etc.) real-time from the drone to the ground station, large transmission rates are required. The PA is a key element in the transmitter chain to guarantee the data transmission (video, photo, etc.) over a long range from the ground station. The more linear output power, the better the coverage or alternatively, with the same coverage, better SNR allows the use of high-order modulation schemes and thus higher transmission rates are achieved. In the context of UAV wireless communications, the power consumption, size and weight of the payload is of significant importance. Therefore, the PA design has to take into account the compromise among bandwidth, output power, linearity and power efficiency (very critical in battery-supplied devices). The PA can be designed to maximize its power efficiency or its linearity, but not both. Therefore, a way to deal with this inherent trade-off is to design high efficient amplification topologies and let the PA linearizers take care of the linearity requirements. Among the linearizers, DPD linearization is the preferred solution to both academia and industry, for its high flexibility and linearization performance. In order to save as many computational and power resources as possible, the implementation of an open-loop DPD results a very attractive solution for UAV applications. This thesis contributes to the PA linearization, especially on off-line training for open-loop DPD, by presenting two different methods for reducing the design and operating costs of an open-loop DPD, based on the analysis of the DPD function. The first method focuses on the input domain analysis, proposing mesh-selecting (MeS) methods to accurately select the proper samples for a computationally efficient DPD parameter estimation. Focusing in the MeS method with better performance, the memory I-Q MeS method is combined with feature extraction dimensionality reduction technique to allow a computational complexity reduction in the identification subsystem by a factor of 65, in comparison to using the classical QR-LS solver and consecutive samples selection. In addition, the memory I-Q MeS method has been proved to be of crucial interest when training artificial neural networks (ANN) for DPD purposes, by significantly reducing the ANN training time. The second method involves the use of machine learning techniques in the DPD design procedure to enlarge the capacity of the DPD algorithm when considering a high number of free parameters to tune. On the one hand, the adaLIPO global optimization algorithm is used to find the best parameter configuration of a generalized memory polynomial behavioral model for DPD. On the other hand, a methodology to conduct a global optimization search is proposed to find the optimum values of a set of key circuit and system level parameters, that properly combined with DPD linearization and crest factor reduction techniques, can exploit at best dual-input PAs in terms of maximizing power efficiency along wide bandwidths while being compliant with the linearity specifications. The advantages of these proposed techniques have been validated through experimental tests and the obtained results are analyzed and discussed along this thesis.Aquesta tesi doctoral proporciona unes pautes per al disseny de linealitzadors basats en predistorsió digital (DPD) des de diverses perspectives: i) millorar el rendiment del DPD en llaç obert, ii) proporcionar robustesa i reduir la complexitat computacional del subsistema d'identificació de paràmetres i, iii) incorporació de tècniques d'aprenentatge automàtic per afavorir l'auto-ajustament d'amplificadors de potència (PAs) i linealitzadors DPD amb diversos graus de llibertat per poder maximitzar l’eficiència energètica i al mateix temps acomplir amb les especificacions de linealitat. Una de les parts essencials dels vehicles aeris no tripulats (UAV) _es l’aviònica, sent el radiocontrol un dels primers sistemes presents als UAV. Per transferir dades d'usuari (com ara imatges, vídeo, etc.) en temps real des del dron a l’estació terrestre, es requereixen taxes de transmissió grans. El PA _es un element clau de la cadena del transmissor per poder garantir la transmissió de dades a grans distàncies de l’estació terrestre. A major potència de sortida, més cobertura o, alternativament, amb la mateixa cobertura, millor relació senyal-soroll (SNR) la qual cosa permet l’ús d'esquemes de modulació d'ordres superiors i, per tant, aconseguir velocitats de transmissió més altes. En el context de les comunicacions sense fils en UAVs, el consum de potència, la mida i el pes de la càrrega útil són de vital importància. Per tant, el disseny del PA ha de tenir en compte el compromís entre ample de banda, potència de sortida, linealitat i eficiència energètica (molt crític en dispositius alimentats amb bateries). El PA es pot dissenyar per maximitzar la seva eficiència energètica o la seva linealitat, però no totes dues. Per tant, per afrontar aquest compromís s'utilitzen topologies amplificadores d'alta eficiència i es deixa que el linealitzador s'encarregui de garantir els nivells necessaris de linealitat. Entre els linealitzadors, la linealització DPD és la solució preferida tant per al món acadèmic com per a la indústria, per la seva alta flexibilitat i rendiment. Per tal d'estalviar tant recursos computacionals com consum de potència, la implementació d'un DPD en lla_c obert resulta una solució molt atractiva per a les aplicacions UAV. Aquesta tesi contribueix a la linealització del PA, especialment a l'entrenament fora de línia de linealitzadors DPD en llaç obert, presentant dos mètodes diferents per reduir el cost computacional i augmentar la fiabilitat dels DPDs en llaç obert. El primer mètode se centra en l’anàlisi de l’estadística del senyal d'entrada, proposant mètodes de selecció de malla (MeS) per seleccionar les mostres més significatives per a una estimació computacionalment eficient dels paràmetres del DPD. El mètode proposat IQ MeS amb memòria es pot combinar amb tècniques de reducció del model del DPD i d'aquesta manera poder aconseguir una reducció de la complexitat computacional en el subsistema d’identificació per un factor de 65, en comparació amb l’ús de l'algoritme clàssic QR-LS i selecció de mostres d'entrenament consecutives. El segon mètode consisteix en l’ús de tècniques d'aprenentatge automàtic pel disseny del DPD quan es considera un gran nombre de graus de llibertat (paràmetres) per sintonitzar. D'una banda, l'algorisme d’optimització global adaLIPO s'utilitza per trobar la millor configuració de paràmetres d'un model polinomial amb memòria generalitzat per a DPD. D'altra banda, es proposa una estratègia per l’optimització global d'un conjunt de paràmetres clau per al disseny a nivell de circuit i sistema, que combinats amb linealització DPD i les tècniques de reducció del factor de cresta, poden maximitzar l’eficiència de PAs d'entrada dual de gran ample de banda, alhora que compleixen les especificacions de linealitat. Els avantatges d'aquestes tècniques proposades s'han validat mitjançant proves experimentals i els resultats obtinguts s'analitzen i es discuteixen al llarg d'aquesta tesi

Advanced signal processing techniques for the modeling and linearization of wireless communication systems.

Los nuevos estándares de comunicaciones digitales inalámbricas están impulsando el diseño de amplificadores de potencia con unas condiciones límites en términos de linealidad y eficiencia. Si bien estos nuevos sistemas exigen que los dispositivos activos trabajen cerca de la zona de saturación en busca de la eficiencia energética, la no linealidad inherente puede producir que el sistema muestre prestaciones inadecuadas en emisiones fuera de banda y distorsión en banda. La necesidad de técnicas digitales de compensación y la evolución en el diseño de nuevas arquitecturas de procesamiento de señales digitales posicionan a la predistorsión digital (DPD) como un enfoque práctico. Los predistorsionadores digitales se suelen basar en modelos de comportamiento como el memory polynomial (MP), el generalized memory polynomial (GMP) y el dynamic deviation reduction-based (DDR), etc. Los modelos de Volterra sufren la llamada "maldición de la dimensionalidad", ya que su complejidad tiende a crecer de forma exponencial a medida que el orden y la profundidad de memoria crecen. Esta tesis se centra principalmente en contribuir a la rama de conocimiento que enmarca el modelado y linealización de sistemas de comunicación inalámbrica. Los principales temas tratados son el modelo Volterra-Parafac y el modelo general de Volterra para sistemas complejos, los cuales tratan la estructura del DPD y las series de Volterra estructuradas con compressed-sensing y un método para la linealización en un rango de potencias de operación, que se centran en cómo los coeficientes de los modelos deben ser obtenidos.Premio Extraordinario de Doctorado U

Transformer NN-based behavioral modeling and predistortion for wideband pas

Abstract. This work investigates the suitability of transformer neural networks (NNs) for behavioral modeling and the predistortion of wideband power amplifiers. We propose an augmented real-valued time delay transformer NN (ARVTDTNN) model based on a transformer encoder that utilizes the multi-head attention mechanism. The inherent parallelized computation nature of transformers enables faster training and inference in the hardware implementation phase. Additionally, transformers have the potential to learn complex nonlinearities and long-term memory effects that will appear in future high-bandwidth power amplifiers. The experimental results based on 100 MHz LDMOS Doherty PA show that the ARVTDTNN model exhibits superior or comparable performance to the state-of-the-art models in terms of normalized mean square error (NMSE) and adjacent channel power ratio (ACPR). It improves the NMSE and ACPR up to −37.6 dB and −41.8 dB, respectively. Moreover, this approach can be considered as a generic framework to solve sequence-to-one regression problems with the transformer architecture

The digital predistorter goes multi-dimensional: DPD for concurrent multi-band envelope tracking and outphasing power amplifiers

Over at least the last two decades, digital predistortion (DPD) has become the most common and widespread solution to cope with the power amplifier's (PA's) inherent linearity-versus-efficiency tradeoff. When compared with other linearization techniques, such as Cartesian feedback or feedforward, DPD has proven able to adapt to the always-growing demands of technology: wider bandwidths, stringent spectrum masks, and reconfigurability. The principles of predistortion linearization (in its analog or digital forms) are straightforward, and the linearization subsystem precedes the PA (a nonlinear function in a digital signal processor in the case of DPD or nonlinear device in the case of analog predistortion and counteracts the nonlinear characteristic of the PA. Some excellent overviews on DPD can be found in [1]-[4]. Let us now look at the challenges that DPD linearization has faced and will continue to face in the near future with 5G new radio (5G-NR).This work has been supported in part by the Spanish Government and FEDER under MICINN projects TEC2017-83343-C4-1-R and TEC2017-83343-C4-2-R and by the Generalitat de Catalunya under Grant 2017 SGR 813

Design and linearization of an efficient class E power amplifier using a test bench based on development boards

Nowadays, with the increase in small satellites applications for Earth observation, the need for high efficient transmitters capable of delivering the required power, taking into account not only the power consumption limitations of small satellites (solar powered), but also the required linearity to allow high data rates in the downlink, has fostered the research on alternatives to the classical transmitter amplification. This Master Thesis has the objective to mitigate the inherent trade-off between linearity and efficiency in communication transmitters by addressing the design of an efficient Power Amplifier (PA) combined with the implementation of Crest Factor Reduction (CFR) and Digital Predistortion (DPD) techniques. For this purpose, the deployment of a low-budget test bench based on development boards is proposed to carry out the PA evaluation and linearization avoiding the use of expensive laboratory equipment for signal generation and analysis. The experimental campaign was carried out using CFR technique to limit the Peak to Average Power Ratio (PAPR) in addition to the DPD linearization, this method not only allowed us to reduce spectral regrowth and minimize in-band distortion, but also was a crucial approach to maximize power amplifier efficiency fulfilling the linearity requirement imposed by the communications standards. The evaluation of the class-E PA designed (under the supervision of the Communication Engineering research group of the University of Cantabria) was performed using a LTE-like signal of 20 MHz employing Quadrature Amplitude Modulation (QAM) and Orthogonal Frequency-Division Multiplexing (OFDM). The measurements shown that it is possible to achieve an output power of 36,6 dBm with an efficiency about 50% in contrast to the typical class-AB PA efficiency figures ranging from 5-10% when operated with significant back-off levels to avoid saturation. Moreover, the Adjacent Channel Power Ratio (ACPR) is below -45 dB and the Error Vector Magnitude (EVM) is around 1,4% for a 64QAM signal in compliance with the communication standards