'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Abstract
This paper presents a hardware implementation of
a digital predistorter (DPD) for linearizing RF power amplifiers
(PAs) for wideband applications. The proposed predistortion linearizer
is based on a nonlinear auto-regressive moving average
(NARMA) structure, which can be derived from the NARMA PA
behavioral model and then mapped into a set of scalable lookup
tables (LUTs). The linearizer takes advantage of its recursive nature
to relax the LUT count needed to compensate memory effects
in PAs. Experimental support is provided by the implementation
of the proposed NARMA DPD in a field-programmable gate-array
device to linearize a 170-W peak power PA, validating the recursive
DPD NARMA structure for W-CDMA signals and flexible transmission
bandwidth scenarios. To the best of the authors’ knowledge,
it is the first time that a recursive structure is experimentally
validated for DPD purposes. In addition to the results on PA efficiency
and linearity, this paper addresses many practical implementation
issues related to the use of FPGA in DPD applications,
giving an original insight on actual prototyping scenarios. Finally,
this study discusses the possibility of further enhancing the overall
efficiency by degrading the PA operation mode, provided that DPD
may be unavoidable due to the impact of memory effects.Peer Reviewe
