Development and Deployment of VoiceXML-Based Banking Applications

In recent times, the financial sector has become one of the most vibrant sectors of the Nigerian economy with about twenty five banks after the bank consolidation / merger exercise. This sector presents huge business investments in the area of Information and Communication Technology (ICT). It is also plausible to say that the sector today is the largest body of ICT services and products users. It is no gainsaying the fact that so many Nigerians now carry mobile phones across the different parts of the country. However, applications that provide voice access to real-time banking transactions from anywhere, anytime via telephone are still at their very low stage of adoption across the Nigerian banking and financial sector. A versatile speech-enabled mobile banking application has been developed using VXML, PHP, Apache and MySQL. The developed application provides real-time access to banking services, thus improving corporate bottom-line and Quality of Service (QoS) for customer satisfaction

BRAHMS: Novel middleware for integrated systems computation

Biological computational modellers are becoming increasingly interested in building large, eclectic models, including components on many different computational substrates, both biological and non-biological. At the same time, the rise of the philosophy of embodied modelling is generating a need to deploy biological models as controllers for robots in real-world environments. Finally, robotics engineers are beginning to find value in seconding biomimetic control strategies for use on practical robots. Together with the ubiquitous desire to make good on past software development effort, these trends are throwing up new challenges of intellectual and technological integration (for example across scales, across disciplines, and even across time) - challenges that are unmet by existing software frameworks. Here, we outline these challenges in detail, and go on to describe a newly developed software framework, BRAHMS. that meets them. BRAHMS is a tool for integrating computational process modules into a viable, computable system: its generality and flexibility facilitate integration across barriers, such as those described above, in a coherent and effective way. We go on to describe several cases where BRAHMS has been successfully deployed in practical situations. We also show excellent performance in comparison with a monolithic development approach. Additional benefits of developing in the framework include source code self-documentation, automatic coarse-grained parallelisation, cross-language integration, data logging, performance monitoring, and will include dynamic load-balancing and 'pause and continue' execution. BRAHMS is built on the nascent, and similarly general purpose, model markup language, SystemML. This will, in future, also facilitate repeatability and accountability (same answers ten years from now), transparent automatic software distribution, and interfacing with other SystemML tools. (C) 2009 Elsevier Ltd. All rights reserved

Software Defined Networks based Smart Grid Communication: A Comprehensive Survey

The current power grid is no longer a feasible solution due to ever-increasing user demand of electricity, old infrastructure, and reliability issues and thus require transformation to a better grid a.k.a., smart grid (SG). The key features that distinguish SG from the conventional electrical power grid are its capability to perform two-way communication, demand side management, and real time pricing. Despite all these advantages that SG will bring, there are certain issues which are specific to SG communication system. For instance, network management of current SG systems is complex, time consuming, and done manually. Moreover, SG communication (SGC) system is built on different vendor specific devices and protocols. Therefore, the current SG systems are not protocol independent, thus leading to interoperability issue. Software defined network (SDN) has been proposed to monitor and manage the communication networks globally. This article serves as a comprehensive survey on SDN-based SGC. In this article, we first discuss taxonomy of advantages of SDNbased SGC.We then discuss SDN-based SGC architectures, along with case studies. Our article provides an in-depth discussion on routing schemes for SDN-based SGC. We also provide detailed survey of security and privacy schemes applied to SDN-based SGC. We furthermore present challenges, open issues, and future research directions related to SDN-based SGC.Comment: Accepte

Towards Viable Large Scale Heterogeneous Wireless Networks

We explore radio resource allocation and management issues related to a large-scale heterogeneous (hetnet) wireless system made up of several Radio Access Technologies (RATs) that collectively provide a unified wireless network to a diverse set of users through co-ordination managed by a centralized Global Resource Controller (GRC). We incorporate 3G cellular technologies HSPA and EVDO, 4G cellular technologies WiMAX and LTE, and WLAN technology Wi-Fi as the RATs in our hetnet wireless system. We assume that the user devices are either multi-modal or have one or more reconfigurable radios which makes it possible for each device to use any available RAT at any given time subject to resource-sharing agreements. For such a hetnet system where resource allocation is coordinated at a global level, characterizing the network performance in terms of various conflicting network efficiency objectives that takes costs associated with a network re-association operation into account largely remains an open problem. Also, all the studies to-date that try to characterize the network performance of a hetnet system do not account for RAT-specific implementation details and the management overhead associated with setting up a centralized control. We study the radio resource allocation problem and the implementation/management overhead issues associated with a hetnet system in two research phases. In the first phase, we develop cost models associated with network re-association in terms of increased power consumption and communication downtime taking into account various user device assumptions. Using these cost models in our problem formulations, the first phase focuses on resource allocation strategies where we use a high-level system modeling approach to study the achievable performance in terms of conflicting network efficiency measures of spectral efficiency, overall power consumption, and instantaneous and long-term fairness for each user in the hetnet system. Our main result from this phase of study suggests that the gain in spectral efficiency due to multi-access network diversity results in a tremendous increase in overall power consumption due to frequent re-associations required by user devices. We then develop a utility function-based optimization algorithm to characterize and achieve a desired tradeoff in terms of all four network efficiency measures of spectral efficiency, overall power consumption and instantaneous and long-term fairness. We show an increase in a multi-attribute system utility measure of up to 56.7% for our algorithm compared to other widely studied resource allocation algorithms including max-sum rate, proportional fairness, max-min fairness and min power. The second phase of our research study focuses on practical implementation issues including the overhead required to implement a centralized GRC solution in a hetnet system. Through detailed protocol level simulations performed in ns-2, we show an increase in spectral efficiency of up to 99% and an increase in instantaneous fairness of up to 28.5% for two sort-based user device-to-Access Point (AP)/Base Station (BS) association algorithms implemented at the GRC that aim to maximize system spectral efficiency and instantaneous fairness performance metrics respectively compared to a distributed solution where each user makes his/her own association decision. The efficiency increase for each respective attribute again results in a tremendous increase in power consumption of up to 650% and 794% for each respective algorithm implemented at the GRC compared to a distributed solution because of frequent re-associations

FPGA Accelerators on Heterogeneous Systems: An Approach Using High Level Synthesis

La evolución de las FPGAs como dispositivos para el procesamiento con alta eficiencia energética y baja latencia de control, comparada con dispositivos como las CPUs y las GPUs, las han hecho atractivas en el ámbito de la computación de alto rendimiento (HPC).A pesar de las inumerables ventajas de las FPGAs, su inclusión en HPC presenta varios retos. El primero, la complejidad que supone la programación de las FPGAs comparada con dispositivos como las CPUs y las GPUs. Segundo, el tiempo de desarrollo es alto debido al proceso de síntesis del hardware. Y tercero, trabajar con más arquitecturas en HPC requiere el manejo y la sintonización de los detalles de cada dispositivo, lo que añade complejidad.Esta tesis aborda estos 3 problemas en diferentes niveles con el objetivo de mejorar y facilitar la adopción de las FPGAs usando la síntesis de alto nivel(HLS) en sistemas HPC.En un nivel próximo al hardware, en esta tesis se desarrolla un modelo analítico para las aplicaciones limitadas en memoria, que es una situación común en aplicaciones de HPC. El modelo, desarrollado para kernels programados usando HLS, puede predecir el tiempo de ejecución con alta precisión y buena adaptabilidad ante cambios en la tecnología de la memoria, como las DDR4 y HBM2, y en las variaciones en la frecuencia del kernel. Esta solución puede aumentar potencialmente la productividad de las personas que programan, reduciendo el tiempo de desarrollo y optimización de las aplicaciones.Entender los detalles de bajo nivel puede ser complejo para las programadoras promedio, y el desempeño de las aplicaciones para FPGA aún requiere un alto nivel en las habilidades de programación. Por ello, nuestra segunda propuesta está enfocada en la extensión de las bibliotecas con una propuesta para cómputo en visión artificial que sea portable entre diferentes fabricantes de FPGAs. La biblioteca se ha diseñado basada en templates, lo que permite una biblioteca que da flexibilidad a la generación del hardware y oculta decisiones de diseño críticas como la comunicación entre nodos, el modelo de concurrencia, y la integración de las aplicaciones en el sistema heterogéneo para facilitar el desarrollo de grafos de visión artificial que pueden ser complejos.Finalmente, en el runtime del host del sistema heterogéneo, hemos integrado la FPGA para usarla de forma trasparente como un dispositivo acelerador para la co-ejecución en sistemas heterogéneos. Hemos hecho una serie propuestas de altonivel de abstracción que abarca los mecanismos de sincronización y políticas de balanceo en un sistema altamente heterogéneo compuesto por una CPU, una GPU y una FPGA. Se presentan los principales retos que han inspirado esta investigación y los beneficios de la inclusión de una FPGA en rendimiento y energía.En conclusión, esta tesis contribuye a la adopción de las FPGAs para entornos HPC, aportando soluciones que ayudan a reducir el tiempo de desarrollo y mejoran el desempeño y la eficiencia energética del sistema.---------------------------------------------The emergence of FPGAs in the High-Performance Computing domain is arising thanks to their promise of better energy efficiency and low control latency, compared with other devices such as CPUs or GPUs.Albeit these benefits, their complete inclusion into HPC systems still faces several challenges. First, FPGA complexity means its programming more difficult compared to devices such as CPU and GPU. Second, the development time is longer due to the required synthesis effort. And third, working with multiple devices increments the details that should be managed and increase hardware complexity.This thesis tackles these 3 problems at different stack levels to improve and to make easier the adoption of FPGAs using High-Level Synthesis on HPC systems. At a close to the hardware level, this thesis contributes with a new analytical model for memory-bound applications, an usual situation for HPC applications. The model for HLS kernels can anticipate application performance before place and route, reducing the design development time. Our results show a high precision and adaptable model for external memory technologies such as DDR4 and HBM2, and kernel frequency changes. This solution potentially increases productivity, reducing application development time.Understanding low-level implementation details is difficult for average programmers, and the development of FPGA applications still requires high proficiency program- ming skills. For this reason, the second proposal is focused on the extension of a computer vision library to be portable among two of the main FPGA vendors. The template-based library allows hardware flexibility and hides design decisions such as the communication among nodes, the concurrency programming model, and the application’s integration in the heterogeneous system, to develop complex vision graphs easily.Finally, we have transparently integrated the FPGA in a high level framework for co-execution with other devices. We propose a set of high level abstractions covering synchronization mechanism and load balancing policies in a highly heterogeneous system with CPU, GPU, and FPGA devices. We present the main challenges that inspired this research and the benefits of the FPGA use demonstrating performance and energy improvements.<br /

10281 Abstracts Collection -- Dynamically Reconfigurable Architectures

From 11.07.10 to 16.07.10, Dagstuhl Seminar 10281 ``Dynamically Reconfigurable Architectures \u27\u27 was held in Schloss Dagstuhl~--~Leibniz Center for Informatics. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available

Developing A Medium-Voltage Three-Phase Current Compensator Using Modular Switching Positions

The objective of this thesis is to present the context, application, theory, design, construction, and testing of a proposed solution to unbalanced current loading on three-phase four-wire systems. This solution, known as the Medium-Voltage Unbalanced Current Static Compensator or MV-UCSC, is designed to recirculate currents between the three phases of adistribution system. Through this redistribution of the currents negative- and zero-sequence current components are eliminated and a balanced load is seen upstream from the point of installation. The MV-UCSC as it operates in the distribution system is presented followed by its effect on traditional compensation equipment. The construction of the MV-UCSC as well as 13.8 kV simulations are then shown. Development of the switching positions required by the MVUCSC is then given followed by a variation on this switching position with the intent to reduce part count. Finally, the testing the 13.8 kV three-phase four-wire, neutral-point-clamped, elevenlevel, flying-capacitor-based MV-UCSC connected directly to the grid is presented