A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing

This paper presents a low-phase-noise LC voltage-controlled oscillator (LC-VCO) with top resistive biasing in subthreshold region. The subthreshold LC-VCO has low-power and low-phase-noise due to its high transconductance efficiency and low gate bias condition. The top resistive biasing has more benefit with the feature of phase noise than MOS current source since it can support the low-noise characteristics and large output swing. The LC-VCO designed in 130-nm CMOS process with 0.7-V supply voltage achieves phase noise of -116 dBc/Hz at 200 kHz offset with tuning range of 398 MHz to 408 MHz covering medical implant communication service (MICS) band

Design and realization of fully integrated multiband and multistandard bi-cmos sigma delta frequency synthesizer

Wireless communication has grown, exponentially, with wide range of applications offered for the customers. Among these, WLAN (2.4-2.5GHz, 3.6-3.7GHzand 4.915- 5.825GHz GHz), Bluetooth (2.4 GHz), and WiMAX (2.500-2.696 GHz, 3.4-3.8 GHz and 5.725-5.850 GHz) communication standard/technologies have found largest use local area, indoor – outdoor communication and entertainment system applications. One of the recent trends in this area of technology is to utilize compatible standards on a single chip solutions, while meeting the requirements of each, to provide customers systems with smaller size, lower power consumption and cheaper in cost. In this thesis, RF – Analog, and – Digital Integrated Circuit design methodologies and techniques are applied to realize a multiband / standart (WLAN and WiMAX) operation capable Voltage- Controlled-Oscillator (VCO) and Frequency Synthesizer. Two of the major building blocks of wireless communication systems are designed using 0.35 μm, AMS-Bipolar (HBT)-CMOS process technology. A new inductor switching concept is implemented for providing the multiband operation capability. Performance parameters such as operating frequencies, phase noise, power consumption, and tuning range are modeled and simulated using analytical approaches, ADS® and Cadence® design and simulation environments. Measurement and/or Figure-of-Merit (FOM) values of our circuits have revealed results that are comparable with already published data, using the similar technology, in the literature, indicating the strength of the design methodologies implemented in this study

準ミリ波・ミリ波領域における低位相雑音電圧制御発振器のLC共振器に関する研究

2017岡山県立大学大学

On-chip ultra-fast data acquisition system for optical scanning acoustic microscopy using 0.35um CMOS technology

Optical Scanning Acoustic Microscopy (OSAM) is a non-contacting method of investigating the properties and hidden faults of solid materials. This thesis presents an ultra-fast data acquisition system (DAQ) which samples and digitises the output signal of OSAM. The author's work includes the design of the clock source and the sampler, and integration of the whole system. The clock source is a unique pulse generator based on a 2.624GHz PLL with a Quadrature VCO (QVCO), which is able to generate 4 clock signals in accurate quadrature phase difference. The pulse generator used the 4-phase clocks to provide control pulses to the sampler. The pulses were carefully aligned to the clock edges by digital logic, so that jitters were reduced as much as possible. The required short time delay for the sampler was also provided by the pulse generator, and this was implemented by a smartly-controlled switch box which re-shuffles the 4-phase clocks. The presented sampler is a novel 10.496GSample/s Sub-Sampling Sample-and-Hold Amplifier (SHA). The SHA sampled the input, and transformed its spectrum down to a low-frequency range so that it can be digitised. Charge-domain sampling strategy and double differential switches were both developed in this circuit to significantly improve the sampling speed. The periodicity of the system input was exploited in repetitive sampling to reduce the noise. These designed modules were integrated into a DAQ for a 2x8 sensor array. A pseudo-parallel scanning strategy was presented to minimise the power consumption, and a current-based buffer was applied to deliver the control pulses into the array. The DAQ was implemented on-chip in a low-cost 0.35um standard CMOS process. The measurement results showed that the DAQ successfully achieved a sampling rate more than 10GS/s, with a maximum output resolution of approximately 6 bits

On-chip ultra-fast data acquisition system for optical scanning acoustic microscopy using 0.35um CMOS technology

Optical Scanning Acoustic Microscopy (OSAM) is a non-contacting method of investigating the properties and hidden faults of solid materials. This thesis presents an ultra-fast data acquisition system (DAQ) which samples and digitises the output signal of OSAM. The author's work includes the design of the clock source and the sampler, and integration of the whole system. The clock source is a unique pulse generator based on a 2.624GHz PLL with a Quadrature VCO (QVCO), which is able to generate 4 clock signals in accurate quadrature phase difference. The pulse generator used the 4-phase clocks to provide control pulses to the sampler. The pulses were carefully aligned to the clock edges by digital logic, so that jitters were reduced as much as possible. The required short time delay for the sampler was also provided by the pulse generator, and this was implemented by a smartly-controlled switch box which re-shuffles the 4-phase clocks. The presented sampler is a novel 10.496GSample/s Sub-Sampling Sample-and-Hold Amplifier (SHA). The SHA sampled the input, and transformed its spectrum down to a low-frequency range so that it can be digitised. Charge-domain sampling strategy and double differential switches were both developed in this circuit to significantly improve the sampling speed. The periodicity of the system input was exploited in repetitive sampling to reduce the noise. These designed modules were integrated into a DAQ for a 2x8 sensor array. A pseudo-parallel scanning strategy was presented to minimise the power consumption, and a current-based buffer was applied to deliver the control pulses into the array. The DAQ was implemented on-chip in a low-cost 0.35um standard CMOS process. The measurement results showed that the DAQ successfully achieved a sampling rate more than 10GS/s, with a maximum output resolution of approximately 6 bits

ULTRA LOW POWER FSK RECEIVER AND RF ENERGY HARVESTER

This thesis focuses on low power receiver design and energy harvesting techniques as methods for intelligently managing energy usage and energy sources. The goal is to build an inexhaustibly powered communication system that can be widely applied, such as through wireless sensor networks (WSNs). Low power circuit design and smart power management are techniques that are often used to extend the lifetime of such mobile devices. Both methods are utilized here to optimize power usage and sources. RF energy is a promising ambient energy source that is widely available in urban areas and which we investigate in detail. A harvester circuit is modeled and analyzed in detail at low power input. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology improves RF to DC energy conversion efficiency. The strategy of co-design of the antenna and the harvester creates opportunities to optimize the system power conversion efficiency. Previous surveys have found that ambient RF energy is spread broadly over the frequency domain; however, here it is demonstrated that it is theoretically impossible to harvest RF energy over a wide frequency band if the ambient RF energy source(s) are weak, owing to the voltage requirements. It is found that most of the ambient RF energy lies in a series of narrow bands. Two different versions of harvesters have been designed, fabricated, and tested. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 1800MHz) at an input power as low as -19dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system. A new phase locked loop based receiver architecture is developed to avoid the significant conversion losses associated with OOK architectures. This also helps to minimize power consumption. A new low power mixer circuit has also been designed, and a detailed analysis is provided. Based on the mixer, a low power phase locked loop (PLL) based receiver has been designed, fabricated and measured. A power management circuit and a low power transceiver system have also been co-designed to provide a system on chip solution. The low power voltage regulator is designed to handle a variety of battery voltage, environmental temperature, and load conditions. The whole system can work with a battery and an application specific integrated circuit (ASIC) as a sensor node of a WSN network

Minimum power design of RF front ends

This thesis describes an investigation into the design of RF front ends with minimum power dissipation. The central question is: "What are the fundamental limits for the power dissipation of telecommunication front ends, and what design procedures can be followed that approach these limits and, at the same time, result in practical circuits?" After a discussion of the state of the art in this area, the elementary operations of a front end are identified. For each of these elementary operations, the fundamental limits for the power dissipation are discussed, divided into technology imposed limits and physics imposed limits. A traditional DECT front end design is used to demonstrate the large difference between the fundamental limits and the power dissipation of existing circuits. To improve this situation, first the optimum distribution of specifications across individual subcircuits needs to be determined, such that the requirements for a specific system can be fulfilled. This is achieved through the introduction of formal transforms of the specifications of subcircuits, which correspond with transforms of the subcircuit itself. Using these transforms, the optimum distribution of gain, noise, linearity and power dissipation can be determined. As it turns out, this optimum distribution can even be represented by a simple, analytical expression. This expression predicts that the power dissipation of the DECT front end can be reduced by a factor of 2.7 through an optimum distribution of the specifications. Using these optimum specifications of the subcircuits, the boundaries for further power dissipation reduction can be determined. This is investigated at the system, circuit and technology level. These insights are used in the design of a 2.5GHz wireless local area network, implemented in an optimized technology ("Silicon on Anything"). The power dissipation of the complete receiver is 3.5mW, more than an order of magnitude below other wireless LAN receivers in recent publications. Finally, the combination of this minimum power design method with a platform based development strategy is discussed