Online Switching Time Monitoring of SiC Devices Using Intelligent Gate Driver for Converter Performance Improvement

Most intelligent gate drivers designed for new state of the art WBG devices typically only focus on protection and driving capabilities of the devices. This paper introduces an intelligent gate driver that incorporates online switching time monitoring of silicon carbide (SiC) devices. For this specific case study, three timing conditions (turn-off delay time, turn-off time, and voltage commutation time) of a SiC phase-leg are online monitored. This online monitoring system is achieved through transient detection circuits and a micro-controller. These timing conditions are then utilized to develop converter-level benefits for a voltage-source inverter application using SiC devices. Junction temperature monitoring is realized through turn-off delay time monitoring. Dead-time optimization is achieved with turn-off time monitoring. Dead-time compensation is obtained with turn-off time and voltage commutation time monitoring. The case study converter assembled for testing purposes is a half-bridge inverter using two SiC devices in a phase-leg configuration. All timing conditions are correctly monitored within reasonable difference of the actual condition time. The half-bridge inverter can operate at 600 V DC input and successfully obtain a junction temperature measurement through monitored turn-off delay time and the calibration curve. In addition, dead-time control is realized to reduce device power loss and improve AC output power quality. Furthermore, the proposed online time monitoring system is board-level integrated with the gate driver and suitable for the chip level integration, enabling this practical approach to be cost-effective for end users

Challenges and New Trends in Power Electronic Devices Reliability

The rapid increase in new power electronic devices and converters for electric transportation and smart grid technologies requires a deepanalysis of their component performances, considering all of the different environmental scenarios, overload conditions, and high stressoperations. Therefore, evaluation of the reliability and availability of these devices becomes fundamental both from technical and economicalpoints of view. The rapid evolution of technologies and the high reliability level offered by these components have shown that estimating reliability through the traditional approaches is difficult, as historical failure data and/or past observed scenarios demonstrate. With the aim topropose new approaches for the evaluation of reliability, in this book, eleven innovative contributions are collected, all focusedon the reliability assessment of power electronic devices and related components

SiC power MOSFETs performance, robustness and technology maturity

Relatively recently, SiC power MOSFETs have transitioned from being a research exercise to becoming an industrial reality. The potential benefits that can be drawn from this technology in the electrical energy conversion domain have been amply discussed and partly demonstrated. Before their widespread use in the field, the transistors need to be thoroughly investigated and later validated for robustness and longer term stability and reliability. This paper proposes a review of commercial SiC power MOSFETs state-of-the-art characteristics and discusses trends and needs for further technology improvements, as well as device design and engineering advancements to meet the increasing demands of power electronics

Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

Measuring Level of Degradation in Power Semiconductor Devices using Emerging Techniques

Title from PDF of title page viewed May 24, 2021Dissertation advisor: Faisal KhanVitaIncludes bibliographical references (page 124-154)Thesis (Ph.D.)--School of Computing and Engineering and Department of Mathematics and Statistics, University of Missouri--Kansas City, 2021High thermal and electrical stress, over a period of time tends to deteriorate the health of power electronic switches. Being a key element in any high-power converter systems, power switches such as insulated-gate bipolar junction transistors (IGBTs) and metal-oxide semiconductor field-effect transistors (MOSFETs) are constantly monitored to predict when and how they might fail. A huge fraction of research efforts involves the study of power electronic device reliability and development of novel techniques with higher accuracy in health estimation of such devices. Until today, no other existing techniques can determine the number of lifted bond wires and their locations in a live IGBT module, although this information is extremely helpful to understand the overall state of health (SOH) of an IGBT power module. Through this research work, two emerging methods for online condition monitoring of power IGBTs and MOSFETs have been proposed. First method is based on reflectometry, more specifically, spread spectrum time domain reflectometry (SSTDR) and second method is based on ultrasound based non-destructive evaluation (NDE). Unlike traditional methods, the proposed methods do not require measuring any electrical parameters (such as voltage or current), therefore, minimizes the measurement error. In addition, both of these methods are independent of the operating points of the converter which makes the application of these methods more feasible for any field application. As part of the research, the RL-equivalent circuit to represent the bond wires of an IGBT module has been developed for the device under test. In addition, an analytical model of ultrasound interaction with the bond wires has been derived in order to efficiently detect the bond wire lift offs within the IGBT power module. Both of these methods are equally applicable to the wide band gap (WBG) power devices and power converters. The successful implementation of these methods creates a provision for condition monitoring (CM) hardware embedded gate driver module which will significantly reduce the overall health monitoring cost.Introduction -- Failure mechanisms of modern power electronic devices -- Existing degradation detection & lifetime prediction techniques -- Accelerated aging methods -- SSTDR based degradation detection -- Ultrasound based degradation -- Degradation detection of wide band gap power devices -- Conclusions and future researc

Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology

Wide bandgap power transistors such as SiC MOSFETs and HEMTs GaN push furthermore the classical compromises in power electronics. Briefly, significant gains have been demonstrated: better efficiency, coupled with an increase in power densities offered by the increase in switching frequency. HV SiC MOSFETs have specific features such as a low short-circuit SC withstand time capability compared to Si IGBTs and thinner gate oxide, and a high gate-to-source switching control voltage. The negative bias on the gate at the off-state creates additional stress which reduces the reliability of the SiC MOSFET. The high positive bias on the gate causes a large drain saturation current in the event of a SC. Thus, this technology gives rise to specific needs for ultrafast monitoring and protection. For this reason, the work of this thesis focuses on two studies to overcome these constraints, with the objective of reaching a good performance compromise between “CMS/ASIC-CMOS technological integration level-speed–robustness”. The first one, gathers a set of new solutions allowing a detection of the SC on the switching cycle, based on a conventional switch control architecture with two voltage levels. The second study is more exploratory and is based on a new gate-driver architecture, called multi-level, with low stress level for the SiC MOSFET while maintaining dynamic performances. The manuscript covers firstly the SiC MOSFET environment, (characterization and properties of SC behavior by simulation using PLECS and LTSpice software) and covers secondly a bibliographical study on the Gate drivers. And last, an in-depth study was carried out on SC type I & II (hard switch fault) (Fault under Load) and their respective detection circuits. A test bench, previously carried out in the laboratory, was used to complete and validate the analysis-simulation study and to prepare test stimuli for the design stage of new solutions. Inspired by the Gate charge method that appeared for Si IGBTs and evoked for SiC MOSFETs, this method has therefore been the subject of design, dimensioning and prototyping work, as a reference. This reference allows an HSF type detection in less than 200ns under 400V with 1.2kV components ranging from 80 to 120mOhm. Regarding new rapid and integrated detection methods, the work of this thesis focuses particularly on the design of a CMOS ASIC circuit. For this, the design of an adapted gate driver is essential. An ASIC is designed in X-Fab XT-0.18 SOICMOS technology under Cadence, and then packaged and assembled on a PCB. The PCB is designed for test needs and adaptable to the main bench. The design of the gate driver considered many functions (SC detection, SSD, segmented buffer, an "AMC", ...). From the SC detection point of view, the new integrated monitoring functions concern the VGS time derivative method which is based on a detection by an RC analog shunt circuit on the plateau sequence with two approaches: the first approach is based on a dip detection, i.e. the presence or not of the Miller plateau. The second approach is based on slope detection, i.e. the variability of the input capacitance of the power transistor under SC-HSF compared to normal operation. These methods are compared in the third chapter of the thesis, and demonstrate fault detection times between 40ns and 80ns, and preliminary robustness studies and critical cases are presented. A second new method is partially integrated in the ASIC, was designed. This method is not developed in the manuscript for valorization purposes. In addition to the main study, an exploratory study has focused on a modular architecture for close control at several bias voltage levels taking advantage of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and improve their reliability through active and dynamic multi-level selection of switching sequences and on/off states