Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions

Physical Computing for Materials Acceleration Platforms

A ''technology lottery'' describes a research idea or technology succeeding over others because it is suited to the available software and hardware, not necessarily because it is superior to alternative directions--examples abound, from the synergies of deep learning and GPUs to the disconnect of urban design and autonomous vehicles. The nascent field of Self-Driving Laboratories (SDL), particularly those implemented as Materials Acceleration Platforms (MAPs), is at risk of an analogous pitfall: the next logical step for building MAPs is to take existing lab equipment and workflows and mix in some AI and automation. In this whitepaper, we argue that the same simulation and AI tools that will accelerate the search for new materials, as part of the MAPs research program, also make possible the design of fundamentally new computing mediums. We need not be constrained by existing biases in science, mechatronics, and general-purpose computing, but rather we can pursue new vectors of engineering physics with advances in cyber-physical learning and closed-loop, self-optimizing systems. Here we outline a simulation-based MAP program to design computers that use physics itself to solve optimization problems. Such systems mitigate the hardware-software-substrate-user information losses present in every other class of MAPs and they perfect alignment between computing problems and computing mediums eliminating any technology lottery. We offer concrete steps toward early ''Physical Computing (PC) -MAP'' advances and the longer term cyber-physical R&D which we expect to introduce a new era of innovative collaboration between materials researchers and computer scientists

On algorithmic rate-coded AER generation

This paper addresses the problem of converting a conventional video stream based on sequences of frames into the spike event-based representation known as the address-event-representation (AER). In this paper we concentrate on rate-coded AER. The problem is addressed as an algorithmic problem, in which different methods are proposed, implemented and tested through software algorithms. The proposed algorithms are comparatively evaluated according to different criteria. Emphasis is put on the potential of such algorithms for a) doing the frame-based to event-based representation in real time, and b) that the resulting event streams ressemble as much as possible those generated naturally by rate-coded address-event VLSI chips, such as silicon AER retinae. It is found that simple and straightforward algorithms tend to have high potential for real time but produce event distributions that differ considerably from those obtained in AER VLSI chips. On the other hand, sophisticated algorithms that yield better event distributions are not efficient for real time operations. The methods based on linear-feedback-shift-register (LFSR) pseudorandom number generation is a good compromise, which is feasible for real time and yield reasonably well distributed events in time. Our software experiments, on a 1.6-GHz Pentium IV, show that at 50% AER bus load the proposed algorithms require between 0.011 and 1.14 ms per 8 bit-pixel per frame. One of the proposed LFSR methods is implemented in real time hardware using a prototyping board that includes a VirtexE 300 FPGA. The demonstration hardware is capable of transforming frames of 64 times; 64 pixels of 8-bit depth at a frame rate of 25 frames per second, producing spike events at a peak rate of 107 events per second.European Union IST-2001-34124Gobierno de España TIC-2000-0406-P4, TIC-2003-08164-C03-0

Efficient optimization methods for analog/mixed-signal integrated circuits via machine learning

During the analog design process, a significant amount of human effort is spent on optimizing circuit specifications by tuning the device parameters. Sizing device parameters is the task of obtaining satisfactory performance for certain constraint metrics and minimizing/maximizing other objective metrics. In general, an initial optimization is conducted based on schematic-level electrical simulations. However, the Analog/Mixed-Signal (AMS) Integrated Circuits (IC) design is also sensitive to the parasitics introduced during the layout. Therefore, a more comprehensive approach is to size device parameters under the consideration of layout parasitics. To automate this process, many automation methods are proposed where simulation feedback is integrated into the automation loop for an accurate evaluation of design choices. AMS simulations are typically costly to run; therefore, the automation method's cost is crucial. This dissertation proposes efficient automated solutions to solve the AMS sizing problem. First, this dissertation proposes a novel Machine Learning (ML) assisted evolutionary algorithm to tackle analog sizing problem. We address the data scarcity issue by introducing a data augmentation method that facilitates and improves the modeling of design metrics via Artificial Neural Networks (ANN). Further, we borrow techniques developed for evolutionary algorithms and introduce a parameter-free ranking methodology to differentiate design performance without human input. We assess the performance of our approach on several academic circuits and show that ML-based modeling significantly improves the simulation cost of the optimization algorithm. Second, in this dissertation, we study applying Reinforcement Learning~(RL) to solve analog sizing problem. We are influenced by the state-of-the-art policy gradient methods and tailor them to solve analog sizing task. Further, we include a recipe to extend this method for solving industrial-scale circuits with thousands of devices. We demonstrate the performance of our approach both on academic circuits and industrial circuits. We observe a significant performance improvement compared to several conventional baseline algorithms and compared to existing commercial tools. Then we visit the AMS tasks with varying simulations costs. Motivated by the fact that one typically needs to run multiple types of simulations, we leverage cheap-to-run simulations to make intermediate decisions on the potential quality of explored points. Then we refrain from expensive-to-run simulations if necessary. In addition, we introduce an asynchronously parallel framework and adapt our previous work for the case of designs with the differentiated cost of simulations. Our benchmarking shows that the proposed methods significantly reduce the total real-time optimization cost and the total CPU effort. Finally, this dissertation includes a solution on how to solve the sizing problem under layout effects effectively. We conduct a study to quantify the impacts of considering layout during transistor sizing. Then, we apply a Bayesian Neural Network~(BNN) based approach to solve the sizing problem. To include layout-induced parasitics, we extend our approach via Multi-Fidelity BNN, where the algorithm utilizes multiple information sources for efficient learning of post-layout performances. We also include a search-space exploration strategy using the trust-region approach, which is shown to be effective on problems with high number of input dimensions. Our tests suggest that the BNN-based sizing algorithm is very competitive compared to previous state-of-the-art algorithms. We further demonstrate that the co-learning strategy of Multi-Fidelity BNN further improves the efficiency, which is very crucial considering the costly post-layout simulations.Electrical and Computer Engineerin

Modeling of the multilevel conduction characteristics and fatigue profile of Ag/La 1/3 Ca 2/3 MnO 3 /Pt structures using a compact memristive approach

The hysteretic conduction characteristics and fatigue profile of La1/3Ca2/3MnO3 (LCMO)-based memristive devices were investigated. The oxide films were grown by pulsed laser deposition (PLD) and sandwiched between Ag and Pt electrodes. The devices exhibit bipolar resistive switching (RS) effect with well-defined intermediate conduction states that arise from partial SET and RESET events. The current-voltage curves are modeled and simulated using a compact memristive approach. Two equations are considered: one for the electron transport based on the double-diode equation and the other for the memory state of the device driven by the play operator with logistic ridge functions. An expression that accounts for the remnant resistance of the device is obtained after simplifying the model equations in the low-voltage limit. The role played by the power dissipation in the LCMO reset dynamics as well as the asymmetrical reduction of the resistance window caused by long trains of switching pulses are discussed.Fil: Miranda, E.. Universidad Autonoma de Barcelona. Facultad de Física; EspañaFil: Roman Acevedo, Wilson Stibens. Comisión Nacional de Energía Atómica. Centro Atómico Constituyentes. Gerencia de Investigación y Aplicaciones; Argentina. Universidad Nacional de San Martín. Escuela de Ciencia y Tecnología; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Rubi, Diego. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad Nacional de San Martín. Escuela de Ciencia y Tecnología; Argentina. Comisión Nacional de Energía Atómica. Centro Atómico Constituyentes. Gerencia de Investigación y Aplicaciones; ArgentinaFil: Lüders, U.. Centre National de la Recherche Scientifique; Francia. École Nationale Supérieure d'Ingénieurs de Caen; FranciaFil: Granell, Pablo Nicolás. Instituto Nacional de Tecnología Industrial. Centro de Micro y Nanoelectrónica del Bicentenario; ArgentinaFil: Suñé, J.. Universidad Autonoma de Barcelona. Facultad de Física; EspañaFil: Levy, Pablo Eduardo. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Comisión Nacional de Energía Atómica. Centro Atómico Constituyentes. Gerencia de Investigación y Aplicaciones; Argentina. Universidad Nacional de San Martín. Escuela de Ciencia y Tecnología; Argentin

The Impact of SAR-ADC Mismatch on Quantized Massive MU-MIMO Systems

Low-resolution analog-to-digital converters (ADCs) in massive multi-user (MU) multiple-input multiple-output (MIMO) wireless systems can significantly reduce the power, cost, and interconnect data rates of infrastructure basestations. Thus, recent research on the theory and algorithm sides has extensively focused on such architectures, but with idealistic quantization models. However, real-world ADCs do not behave like ideal quantizers, and are affected by fabrication mismatches. We analyze the impact of capacitor-array mismatches in successive approximation register (SAR) ADCs, which are widely used in wireless systems. We use Bussgang's decomposition to model the effects of such mismatches, and we analyze their impact on the performance of a single ADC. We then simulate a massive MU-MIMO system to demonstrate that capacitor mismatches should not be ignored, even in basestations that use low-resolution SAR ADCs.Comment: To be presented at Asilomar Conference on Signals, Systems, and Computers 202

Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation

The focus of this thesis is on the development and implementation of aging-aware design methods, which are suitable to satisfy current needs of analog circuit design. Based on the well known \gm/\ID sizing methodology, an innovative tool-assisted aging-aware design approach is proposed, which is able to estimate shifts in circuit characteristics using mostly hand calculation schemes. The developed concept of an operating point-dependent degradation leads to the definition of an aging-aware sensitivity, which is compared to currently available degradation simulation flows and proves to be efficient in the estimation of circuit degradation. Using the aging-aware sensitivity, several analog circuits are investigated and optimized towards higher reliability. Finally, results are presented for numerous target specifications

Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures