2,540 research outputs found
Integrated Circuits for Programming Flash Memories in Portable Applications
Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration
Low-Power and Programmable Analog Circuitry for Wireless Sensors
Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits
Low-Power and Programmable Analog Circuitry for Wireless Sensors
Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits
Non-volatile heterogeneous III-V/Si photonics via optical charge-trap memory
We demonstrate, for the first time, non-volatile charge-trap flash memory
(CTM) co-located with heterogeneous III-V/Si photonics. The wafer-bonded
III-V/Si CTM cell facilitates non-volatile optical functionality for a variety
of devices such as Mach-Zehnder Interferometers (MZIs), asymmetric MZI lattice
filters, and ring resonator filters. The MZI CTM exhibits full write/erase
operation (100 cycles with 500 states) with wavelength shifts of
() and a dynamic power consumption 20 pW (limited by
measurement). Multi-bit write operation (2 bits) is also demonstrated and
verified over a time duration of 24 hours and most likely beyond. The cascaded
2nd order ring resonator CTM filter exhibited an improved ER of ~ 7.11 dB
compared to the MZI and wavelength shifts of () with similar
pW-level dynamic power consumption as the MZI CTM. The ability to co-locate
photonic computing elements and non-volatile memory provides an attractive path
towards eliminating the von-Neumann bottleneck
High-Performance Silicon Nanowire Electronics
This thesis explores 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications via the fabrication and testing of SiNW-based ring oscillators. Both SiNW surface treatments and dielectric annealing are reported for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~108), low drain-induced barrier lowering (~30 mV), high carrier mobilities (~269 cm2/V•s), and low subthreshold swing (~80 mV/dec). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs is explored as well. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.
A set of novel charge-trap non-volatile memory devices based on high-performance SiNW FETs are well investigated. These memory devices integrate Fe2O3 quantum dots (FeO QDs) as charge storage elements. A template-assisted assembly technique is used to align FeO QDs into a close-packed, ordered matrix within the trenches that separate highly aligned SiNWs, and thus store injected charges. A Fowler-Nordheim tunneling mechanism describes both the program and erase operations. The memory prototype demonstrates promising characteristics in terms of large threshold voltage shift (~1.3 V) and long data retention time (~3 × 106 s), and also allows for key components to be systematically varied. For example, varying the size of the QDs indicates that larger diameter QDs exhibit a larger memory window, suggesting the QD charging energy plays an important role in the carrier transport. The device temperature characteristics reveal an optimal window for device performance between 275K and 350K.
The flexibility of integrating the charge-trap memory devices with the SiNW logic devices offers a low-cost embedded non-volatile memory solution. A building block for a SiNW-based field-programmable gate array (FPGA) is proposed in the future work.</p
高密度・高速動作可能なSTT-MRAMへ向けたp-MTJのスイッチング過渡現象とアレイ設計指針に関する研究
Tohoku University遠藤哲郎課
CMOS analog integrated circuit design techniques for low-powered ubiquitous device
制度:新 ; 文部省報告番号:甲2633号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新479
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