Hardware implementations of computer-generated holography: a review

Computer-generated holography (CGH) is a technique to generate holographic interference patterns. One of the major issues related to computer hologram generation is the massive computational power required. Hardware accelerators are used to accelerate this process. Previous publications targeting hardware platforms lack performance comparisons between different architectures and do not provide enough information for the evaluation of the suitability of recent hardware platforms for CGH algorithms. We aim to address these limitations and present a comprehensive review of CGH-related hardware implementations

Generating airborne ultrasonic amplitude patterns using an open hardware phased array

Holographic methods from optics can be adapted to acoustics for enabling novel applications in particle manipulation or patterning by generating dynamic custom-tailored acoustic fields. Here, we present three contributions towards making the field of acoustic holography more widespread. Firstly, we introduce an iterative algorithm that accurately calculates the amplitudes and phases of an array of ultrasound emitters in order to create a target amplitude field in mid-air. Secondly, we use the algorithm to analyse the impact of spatial, amplitude and phase emission resolution on the resulting acoustic field, thus providing engineering insights towards array design. For example, we show an onset of diminishing returns for smaller than a quarter-wavelength sized emitters and a phase and amplitude resolution of eight and four divisions per period, respectively. Lastly, we present a hardware platform for the generation of acoustic holograms. The array is integrated in a single board composed of 256 emitters operating at 40 kHz. We hope that the results and procedures described within this paper enable researchers to build their own ultrasonic arrays and explore novel applications of ultrasonic holograms.This research was funded by the Government of Navarre (FEDER) 0011-1365-2019-000086 and from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 101017746, TOUCHLESS

Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy

This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize throughput of the computation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system

Simulation of an FPGA implementation of holographic video generation in real time

Ankara : The Department of Electrical and Electronics Engineering and the Institute of Engineering and Sciences of Bilkent University, 2010.Thesis (Master's) -- Bilkent University, 2010.Includes bibliographical references leaves 94-97.Holography is a promising method for three-dimensional vision. Different research efforts are being spent to improve generation of holograms and image reconstruction from holograms. A computer generated hologram can be a precise method of generating a real like video in the future. RayleighSommerfeld diffraction method and Fresnel-Kirchhoff diffraction formula are two algorithms suitable for FPGA implementation of hologram calculation. Simulator image reconstructions and optical image reconstructions with spatial light modulator using the generated holograms are compared and it is seen that they are quite similar. A field programmable gate array (FPGA) implementation of real time holographic video generation based on Rayleigh-Sommerfeld formulation is simulated. FPGA implementation is tested and verified by a computer simulator. An FPGA board capable of capturing video input and giving video output for spatial light modulator (SLM) is chosen as the implementation platform for simulations. A small size hologram calculator can be implemented on the FPGA board. A custom board for specific hologram calculation algorithm can be designed to increase the performance. Pipelined architecture and SDRAM memories can be used to increase the performance.Yılmaz, Timur EyüpM.S

Telecommunication Systems

This book is based on both industrial and academic research efforts in which a number of recent advancements and rare insights into telecommunication systems are well presented. The volume is organized into four parts: "Telecommunication Protocol, Optimization, and Security Frameworks", "Next-Generation Optical Access Technologies", "Convergence of Wireless-Optical Networks" and "Advanced Relay and Antenna Systems for Smart Networks." Chapters within these parts are self-contained and cross-referenced to facilitate further study

Modeling and exploration of a reconfigurable architecture for digital holographic imaging

The use of coarse-grain reconfigurable architectures (CGRA) is a suitable alternative for hardware acceleration in many application areas, including digital holographic imaging. In this paper, we propose a CGRA-based system with an array of processing and memory cells, which communicate using a local and a global communication network, and a stream memory controller to manage data transfers to external memory. We present our SystemC-based exploration environment (SCENIC) and methodology used to construct and evaluate systems containing reconfigurable architectures. A case study illustrates the advantages with rapid system level exploration to find and solve bottlenecks in complex designs prior to RTL description

Computer-Generated Holography for Areal Additive Manufacture

With a market of approximately $10B, additive manufacture (AM) is an exciting next-generation technology with the promise of significant environmental and societal impact. AM promises to help reduce emissions and waste during manufacture while improving sustainability. Widely used in applications from hip implants to jet engines, AM remains the domain of experts due to the material and thermal challenges encountered. AM in metals is dominated by Laser Powder Based Fusion (L-PBF). Powder is spread in layers 10s of microns thick and selectively melted by scanning a small laser spot heat source over the bed. Traditional AM systems have limited ability to manage or compensate for heat generated. The rapidly moving heat source spot results in high thermal cycling and is a major influence on residual stress and distortion. Mechanical limitations in the galvoscanner mean that over or under-heating is common and can lead to voids, boiling and spatter. The scale difference between the part size and the spot size means that predictive modelling is beyond the scope of even today’s best computing clusters. These factors have led to frequent inability to ensure part quality without physical prototyping and destructive testing. This thesis sets out initial research into creating a radically new AM process that uses computer-generated holography (CGH) to produce complex light patterns in a single pulse. Projecting power to the whole layer at once will mean that the thermal properties of the powders before and after writing can be factored into the processed hologram and part design. It will also significantly reduce thermal gradients and melt-pool instability. The fields of additive manufacture and computer-generated holography are introduced in Chapter 1. Chapters 2 and 3 then provide more detail on CGH and AM modelling respectively. The first deliverable, a reusable software package capable of generating holograms, is presented in Chapter 4. Algorithms developed for the project are introduced in Chapter 4.3. The first project demonstrator, an AM machine capable of printing in resins using holographic projection is discussed in Section 6.2. This shows performance comparable to modern 3D printing machines and highlights the applicability of computer-generated holography to areal processes. Section 6.3 then discusses the ongoing development of a metal powder demonstrator. As this PhD forms the first stage of a larger project, only preliminary work on the powder demonstrator is discussed. Chapter 7 then draws conclusions and outlines the way forward for future research. The thesis appendices then discuss an in-depth discussion of algorithm performances in Appendices A and B. Appendices C and D then discuss digressions into the implementation. Appendices E and F present a laser induced damage threshold (LIDT) measurement system developed. Finally, Appendices G and H provide more detail on the software developed and Appendix I gives links to additional project resources.EP/T008369/1; EP/L016567/1; EP/V055003/

Multi-Channel Signal Generator ASIC for Acoustic Holograms

A CMOS application-specific integrated circuit (ASIC) has been developed to generate arbitrary, dynamic phase patterns for acoustic hologram applications. An experimental prototype has been fabricated to demonstrate phase shaping. It comprises a cascadable 1 × 9 array of identical, independently-controlled signal generators implemented in a 0.35 μ m minimum feature size process. It can individually control the phase of a square wave on each of the nine output pads. The footprint of the integrated circuit is 1175 × 88 μ m2. A 128 MHz clock frequency is used to produce outputs at 8 MHz with phase resolution of 16 levels (4-bit) per channel. A 6 × 6 air-coupled matrix array ultrasonic transducer was built and driven by four ASICs, with the help of commercial buffer amplifiers, for the application demonstration. Acoustic pressure mapping and particle manipulation were performed. Additionally, a 2 × 2 array piezoelectric micromachined ultrasonic transducer (PMUT) was connected and driven by four output channels of a single ASIC, demonstrating the flexibility of the ASIC to work with different transducers and the potential for direct integration of CMOS and PMUTs