1,746 research outputs found

    An Offset Cancelation Technique for Latch Type Sense Amplifiers

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    An offset compensation technique for a latch type sense amplifier is proposed in this paper. The proposed scheme is based on the recalibration of the charging/discharging current of the critical nodes which are affected by the device mismatches. The circuit has been designed in a 65 nm CMOS technology with 1.2 V core transistors. The auto-calibration procedure is fully digital. Simulation results are given verifying the operation for sampling a 5 Gb/s signal dissipating only 360 uW

    Wide-band mixing DACs with high spectral purity

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    ํŽ„์Šค ๊ธฐ๋ฐ˜ ํ”ผ๋“œ ํฌ์›Œ๋“œ ์ดํ€„๋ผ์ด์ €๋ฅผ ๊ฐ–์ถ˜ ๊ณ ์šฉ๋Ÿ‰ DRAM์„ ์œ„ํ•œ ์ปจํŠธ๋กค๋Ÿฌ PHY ์„ค๊ณ„

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    ํ•™์œ„๋…ผ๋ฌธ (๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2020. 8. ๊น€์ˆ˜ํ™˜.A controller PHY for managed DRAM solution, which is a new memory structure to maximize capacity while minimizing refresh power, is presented. Inter-symbol interference is critical in such a high-capacity DRAM interface in which many DRAM chips share a command/address (C/A) channel. A pulse-based feed-forward equalizer (PB-FFE) is introduced to reduce ISI on a C/A channel. The controller PHY supports all the training sequences specified in the DDR4 standard. A glitch-free DCDL is also adopted to perform link training efficiently and to reduce training time. The DQ transmitter adopts quarter-rate architecture to reduce output latency. For the quarter-rate transmitters in DQ, we propose a quadrature error corrector (QEC), in which clock signal phase errors are corrected using two replicas of the 4:1 serializer of the output stage. Pulse shrinking is used to compare and equalize the outputs of these two replica serializers. A controller PHY was fabricated in 55nm CMOS. The PB-FFE increases the timing margin from 0.23UI to 0.29UI at 1067Mbps. At 2133Mbps, the read timing and voltage margins are 0.53UI and 211mV after read training, and the write margins are 0.72UI and 230mV after write training. To validate the QEC effectiveness, a prototype quarter-rate transmitter, including the QEC, was fabricated to another chip in 65nm CMOS. Adopting our QEC, the experimental results show that the output phase errors of the transmitter are reduced to a residual error of 0.8ps, and the output eye width and height are improved by 84% and 61%, respectively, at a data-rate of 12.8Gbps.๋ณธ ์—ฐ๊ตฌ์—์„œ ์šฉ๋Ÿ‰์„ ์ตœ๋Œ€ํ™”ํ•˜๋ฉด์„œ๋„ ๋ฆฌํ”„๋ ˆ์‹œ ์ „๋ ฅ์„ ์ตœ์†Œํ™”ํ•  ์ˆ˜ ์žˆ๋Š” ์ƒˆ๋กœ์šด ๋ฉ”๋ชจ๋ฆฌ ๊ตฌ์กฐ์ธ ๊ด€๋ฆฌํ˜• DRAM ์†”๋ฃจ์…˜์„ ์œ„ํ•œ ์ปจํŠธ๋กค๋Ÿฌ PHY๋ฅผ ์ œ์‹œํ•˜์˜€๋‹ค. ์ด์™€ ๊ฐ™์€ ๊ณ ์šฉ๋Ÿ‰ DRAM ์ธํ„ฐํŽ˜์ด์Šค์—์„œ๋Š” ๋งŽ์€ DRAM ์นฉ์ด ๋ช…๋ น / ์ฃผ์†Œ (C/A) ์ฑ„๋„์„ ๊ณต์œ ํ•˜๊ณ  ์žˆ์–ด์„œ ์‹ฌ๋ณผ ๊ฐ„ ๊ฐ„์„ญ์ด ๋ฐœ์ƒํ•œ๋‹ค. ๋ณธ ์—ฐ๊ตฌ์—์„œ๋Š” ์ด๋Ÿฌํ•œ C/A ์ฑ„๋„์—์„œ์˜ ์‹ฌ๋ณผ ๊ฐ„ ๊ฐ„์„ญ์„ ์ค„์ด๊ธฐ ์œ„ํ•ด ํŽ„์Šค ๊ธฐ๋ฐ˜ ํ”ผ๋“œ ํฌ์›Œ๋“œ ์ดํ€„๋ผ์ด์ € (PB-FFE)๋ฅผ ์ฑ„ํƒํ•˜์˜€๋‹ค. ๋˜ํ•œ ๋ณธ ์—ฐ๊ตฌ์˜ ์ปจํŠธ๋กค๋Ÿฌ PHY๋Š” DDR4 ํ‘œ์ค€์— ์ง€์ •๋œ ๋ชจ๋“  ํŠธ๋ ˆ์ด๋‹ ์‹œํ€€์Šค๋ฅผ ์ง€์›ํ•œ๋‹ค. ๋งํฌ ํŠธ๋ ˆ์ด๋‹์„ ํšจ์œจ์ ์œผ๋กœ ์ˆ˜ํ–‰ํ•˜๊ณ  ํŠธ๋ ˆ์ด๋‹ ์‹œ๊ฐ„์„ ์ค„์ด๊ธฐ ์œ„ํ•ด ๊ธ€๋ฆฌ์น˜๊ฐ€ ๋ฐœ์ƒํ•˜์ง€ ์•Š๋Š” ๋””์ง€ํ„ธ ์ œ์–ด ์ง€์—ฐ ๋ผ์ธ (DCDL)์„ ์ฑ„ํƒํ•˜์˜€๋‹ค. ์ปจํŠธ๋กค๋Ÿฌ PHY์˜ DQ ์†ก์‹ ๊ธฐ๋Š” ์ถœ๋ ฅ ๋Œ€๊ธฐ ์‹œ๊ฐ„์„ ์ค„์ด๊ธฐ ์œ„ํ•ด ์ฟผํ„ฐ ๋ ˆ์ดํŠธ ๊ตฌ์กฐ๋ฅผ ์ฑ„ํƒํ•˜์˜€๋‹ค. ์ฟผํ„ฐ ๋ ˆ์ดํŠธ ์†ก์‹ ๊ธฐ์˜ ๊ฒฝ์šฐ์—๋Š” ์ง๊ต ํด๋Ÿญ ๊ฐ„ ์œ„์ƒ ์˜ค๋ฅ˜๊ฐ€ ์ถœ๋ ฅ ์‹ ํ˜ธ์˜ ๋ฌด๊ฒฐ์„ฑ์— ์˜ํ–ฅ์„ ์ฃผ๊ฒŒ ๋œ๋‹ค. ์ด๋Ÿฌํ•œ ์˜ํ–ฅ์„ ์ตœ์†Œํ™”ํ•˜๊ธฐ ์œ„ํ•ด ๋ณธ ์—ฐ๊ตฌ์—์„œ๋Š” ์ถœ๋ ฅ ๋‹จ์˜ 4 : 1 ์ง๋ ฌ ๋ณ€ํ™˜๊ธฐ์˜ ๋‘ ๋ณต์ œ๋ณธ์„ ์‚ฌ์šฉํ•˜์—ฌ ํด๋ก ์‹ ํ˜ธ ์œ„์ƒ ์˜ค๋ฅ˜๋ฅผ ์ˆ˜์ •ํ•˜๋Š” QEC (Quadrature Error Corrector)๋ฅผ ์ œ์•ˆํ•˜์˜€๋‹ค. ๋ณต์ œ๋œ 2๊ฐœ์˜ ์ง๋ ฌ ๋ณ€ํ™˜๊ธฐ์˜ ์ถœ๋ ฅ์„ ๋น„๊ตํ•˜๊ณ  ๊ท ๋“ฑํ™”ํ•˜๊ธฐ ์œ„ํ•ด ํŽ„์Šค ์ˆ˜์ถ• ์ง€์—ฐ ๋ผ์ธ์ด ์‚ฌ์šฉ๋˜์—ˆ๋‹ค. ์ปจํŠธ๋กค๋Ÿฌ PHY๋Š” 55nm CMOS ๊ณต์ •์œผ๋กœ ์ œ์กฐ๋˜์—ˆ๋‹ค. PB-FFE๋Š” 1067Mbps์—์„œ C/A ์ฑ„๋„ ํƒ€์ด๋ฐ ๋งˆ์ง„์„ 0.23UI์—์„œ 0.29UI๋กœ ์ฆ๊ฐ€์‹œํ‚จ๋‹ค. ์ฝ๊ธฐ ํŠธ๋ ˆ์ด๋‹ ํ›„ ์ฝ๊ธฐ ํƒ€์ด๋ฐ ๋ฐ ์ „์•• ๋งˆ์ง„์€ 2133Mbps์—์„œ 0.53UI ๋ฐ 211mV์ด๊ณ , ์“ฐ๊ธฐ ํŠธ๋ ˆ์ด๋‹ ํ›„ ์“ฐ๊ธฐ ๋งˆ์ง„์€ 0.72UI ๋ฐ 230mV์ด๋‹ค. QEC์˜ ํšจ๊ณผ๋ฅผ ๊ฒ€์ฆํ•˜๊ธฐ ์œ„ํ•ด QEC๋ฅผ ํฌํ•จํ•œ ํ”„๋กœํ†  ํƒ€์ž… ์ฟผํ„ฐ ๋ ˆ์ดํŠธ ์†ก์‹ ๊ธฐ๋ฅผ 65nm CMOS์˜ ๋‹ค๋ฅธ ์นฉ์œผ๋กœ ์ œ์ž‘ํ•˜์˜€๋‹ค. QEC๋ฅผ ์ ์šฉํ•œ ์‹คํ—˜ ๊ฒฐ๊ณผ, ์†ก์‹ ๊ธฐ์˜ ์ถœ๋ ฅ ์œ„์ƒ ์˜ค๋ฅ˜๊ฐ€ 0.8ps์˜ ์ž”๋ฅ˜ ์˜ค๋ฅ˜๋กœ ๊ฐ์†Œํ•˜๊ณ , ์ถœ๋ ฅ ๋ฐ์ดํ„ฐ ๋ˆˆ์˜ ํญ๊ณผ ๋†’์ด๊ฐ€ 12.8Gbps์˜ ๋ฐ์ดํ„ฐ ์†๋„์—์„œ ๊ฐ๊ฐ 84 %์™€ 61 % ๊ฐœ์„ ๋˜์—ˆ์Œ์„ ๋ณด์—ฌ์ค€๋‹ค.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.1.1 HEAVY LOAD C/A CHANNEL 5 1.1.2 QUARTER-RATE ARCHITECTURE IN DQ TRANSMITTER 7 1.1.3 SUMMARY 8 1.2 THESIS ORGANIZATION 10 CHAPTER 2 ARCHITECTURE 11 2.1 MDS DIMM STRUCTURE 11 2.2 MDS CONTROLLER 15 2.3 MDS CONTROLLER PHY 17 2.3.1 INITIALIZATION SEQUENCE 20 2.3.2 LINK TRAINING FINITE-STATE MACHINE 23 2.3.3 POWER DOWN MODE 28 CHAPTER 3 PULSE-BASED FEED-FORWARD EQUALIZER 29 3.1 COMMAND/ADDRESS CHANNEL 29 3.2 COMMAND/ADDRESS TRANSMITTER 33 3.3 PULSE-BASED FEED-FORWARD EQUALIZER 35 CHAPTER 4 CIRCUIT IMPLEMENTATION 39 4.1 BUILDING BLOCKS 39 4.1.1 ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL) 39 4.1.2 ALL-DIGITAL DELAY-LOCKED LOOP (ADDLL) 44 4.1.3 GLITCH-FREE DCDL CONTROL 47 4.1.4 DUTY-CYCLE CORRECTOR (DCC) 50 4.1.5 DQ/DQS TRANSMITTER 52 4.1.6 DQ/DQS RECEIVER 54 4.1.7 ZQ CALIBRATION 56 4.2 MODELING AND VERIFICATION OF LINK TRAINING 59 4.3 BUILT-IN SELF-TEST CIRCUITS 66 CHAPTER 5 QUADRATURE ERROR CORRECTOR USING REPLICA SERIALIZERS AND PULSE-SHRINKING DELAY LINES 69 5.1 PHASE CORRECTION USING REPLICA SERIALIZERS AND PULSE-SHRINKING UNITS 69 5.2 OVERALL QEC ARCHITECTURE AND ITS OPERATION 71 5.3 FINE DELAY UNIT IN THE PSDL 76 CHAPTER 6 EXPERIMENTAL RESULTS 78 6.1 CONTROLLER PHY 78 6.2 PROTOTYPE QEC 88 CHAPTER 7 CONCLUSION 94 BIBLIOGRAPHY 96Docto

    Integrated Circuit Techniques and Architectures for Beamforming Radio Transmitters

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    Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects

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    Siirretty Doriast

    An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

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    The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

    Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

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    CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

    CMOS Data Converters for Closed-Loop mmWave Transmitters

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    With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2 76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations

    Preliminary candidate advanced avionics system for general aviation

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    An integrated avionics system design was carried out to the level which indicates subsystem function, and the methods of overall system integration. Sufficient detail was included to allow identification of possible system component technologies, and to perform reliability, modularity, maintainability, cost, and risk analysis upon the system design. Retrofit to older aircraft, availability of this system to the single engine two place aircraft, was considered
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