ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters

Versatile standardized pulse modulation nondissipatively regulated control signal processing circuits were applied to three most commonly used dc to dc power converter configurations: (1) the series switching buck-regulator, (2) the pulse modulated parallel inverter, and (3) the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency

Improved Accuracy Area Efficient Hybrid CMOS/GaN DC-DC Buck Converterfor High Step-Down Ratio Applications

abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Variable Spurious Noise Mitigation Techniques in Hysteretic Buck Converters

This work proposes a current-mode hysteretic buck converter with a spur-free constant-cycle frequency-hopping controller that fully eliminates spurs from the switching noise spectrum irrespective of variations in the switching frequency and operating conditions. As a result, the need for frequency regulation loops to ensure non-varying switching frequency (i.e. fixed spurs location) in hysteretic controllers is eliminated. Moreover, compared to frequency regulation loops, the proposed converter offers the advantage of eliminating mixing and interference altogether due to its spur-free operation, and thus, it can be used to power, or to be integrated within noise-sensitive systems while benefiting from the superior dynamic performance of its hysteretic operation. The proposed converter uses dual-sided hysteretic band modulation to eliminate the inductor current imbalance that results from frequency hopping along with the output voltage transients and low-frequency noise floor peaking associated with it. Moreover, a feedforward adaptive hysteretic band controller is proposed to reduce variations in the switching frequency with the input voltage, and an all-digital soft-startup circuit is proposed to control the in-rush current without requiring any off-chip components. The converter is implemented in a 0.35-õm standard CMOS technology and it achieves 92% peak efficiency

Power conversion techniques in nanometer CMOS for low-power applications

As System-on-Chip (SoCs) in nanometer CMOS technologies grow larger, the power management process within these SoCs becomes very challenging. In the heart of this process lies the challenge of implementing energy-efficient and cost-effective DC-DC power converters. To address this challenge, this thesis studies in details three different aspects of DC-DC power converters and proposes potential solutions. First, to maximize power conversion efficiency, loss mechanisms must be studied and quantified. For that purpose, we provide comprehensive analysis and modeling of the various switching and conduction losses in low-power synchronous DC-DC buck converters in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) operation, including the case with non-rail gate control of the power switches. Second, a DC-DC buck converter design with only on-chip passives is proposed and implemented in 65-nm CMOS technology. The converter switches at 588 MHz and uses a 20-nH and 300-pF on-chip inductor and capacitor respectively, and provides up to 30-mA of load at an output voltage in the range of 0.8-1.2 V. The proposed design features over 10% improvement in power conversion efficiency over a corresponding linear regulator while preserving low-cost implementation. Finally, a 40-mA buck converter design operating in the inherently-stable DCM mode for the entire load range is presented. It employs a Pulse Frequency Modulation (PFM) scheme using a Hysteretic-Assisted Adaptive Minimum On-Time (HA-AMOT) controller to automatically adapt to a wide range of operating scenarios while minimizing inductor peak current. As a result, compact silicon area, low quiescent current, high efficiency, and robust performance across all conditions can be achieved without any calibration

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

Design and Control of Power Converters 2019

In this book, 20 papers focused on different fields of power electronics are gathered. Approximately half of the papers are focused on different control issues and techniques, ranging from the computer-aided design of digital compensators to more specific approaches such as fuzzy or sliding control techniques. The rest of the papers are focused on the design of novel topologies. The fields in which these controls and topologies are applied are varied: MMCs, photovoltaic systems, supercapacitors and traction systems, LEDs, wireless power transfer, etc

The presentation of sustainable power source assets in the field of intensity age assumes an imperative job

DC to DC converters to interface lesser-voltage higher-control supply to the essential stock shows the most raised proficiency was practiced in the full-connect converter. Non-separated converters bury unified inductor help converters with essential voltage gain and furthermore converters hold lesser profitability, yet they huge in structure, even the quantity of latent parts is diminished. In like manner gives proficient utilization of semiconductor switches, have higher voltage yield and are prepared to work in lesser estimation of D interestingly with every single disconnected converter. High addition topologies are regularly outfitted with high voltage security structures. Few non-disengaged topologies gives voltage hang security circuits are pointless since capacitive fragments and circuit plan are progressed to work under higher information voltage and low power. That requires lesser qualities for convincing RAC obstruction and entomb partnered inductance dispersal to achieve more prominent adequacy of intensity change. Larger supply current needs extensive region of core area inter allied inductors

Power Converters in Power Electronics

In recent years, power converters have played an important role in power electronics technology for different applications, such as renewable energy systems, electric vehicles, pulsed power generation, and biomedical sciences. Power converters, in the realm of power electronics, are becoming essential for generating electrical power energy in various ways. This Special Issue focuses on the development of novel power converter topologies in power electronics. The topics of interest include, but are not limited to: Z-source converters; multilevel power converter topologies; switched-capacitor-based power converters; power converters for battery management systems; power converters in wireless power transfer techniques; the reliability of power conversion systems; and modulation techniques for advanced power converters

縦型ボディチャネルMOS Field-Effect Transistorを用いたマイクロプロセッサ向け高効率・高集積DC-DCコンバータとそのパワーマネジメントに関する研究

Tohoku University遠藤哲郎課

An improved closed loop hybrid phase shift controller for dual active bridge converter

In this paper, a new closed loop hybrid phase shift control is proposed for dual active bridge (DAB) converter with variable input voltage. The extended phase shift (EPS) control is applied when load gets heavy enough and the secondary side phase shift angle decreases to zero. When this modified DAB converter operates at light loads, the triple phase shift (TPS) modulation method is applied, and the added control freedom is the secondary phase shift angle between the two-secondary side switching legs. The hybrid phase shift control (HPS) scheme is a combination of EPS and TPS modulations, and it provides a very simple closed form implementation for the primary and secondary side phase shift angles. Depending on the application by changing the phase shift angles we can achieve Buck or Boost operation. A characteristic table feedback control method has been used for closed loop operation. By using 1D look up table the proposed DAB converter provides constant 400V for any given input voltage