Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

Interconnect capacitance extraction under geometric uncertainties

Interconnects are an important constituent of any large scale integrated circuit, and accurate interconnect analysis is essential not only for post-layout verification but also for synthesis. For instance, extraction of interconnect capacitance is needed for the prediction of interconnect-induced delay, crosstalk, and other signal distortion related effects that are used to guide IC routing and floor planning. The continuous progress of semiconductor technology is leading ICs to the era of 45 nm technology and beyond. However, this progress has been associated with increasing variability during the manufacturing processes. This variability leads to stochastic variations in geometric and material parameters and has a significant impact on interconnect capacitance. It is therefore important to be able to quantify the effect of such process induced variations on interconnect capacitance. In this thesis, we have worked on a methodology towards modeling of interconnect capacitance in the presence of geometric uncertainties. More specifically, a methodology is proposed for the finite element solution of Laplace's equation for the calculation of the per-unit-length capacitance matrix of a multi-conductor interconnect structure embedded in a multi-layered insulating substrate and in the presence of statistical variation in conductor and substrate geometry. The proposed method is founded on the idea of defining a single, mean geometry, which is subsequently used with a single finite element discretization, to extract the statistics of the interconnect capacitance in an expedient fashion. We demonstrate the accuracy and efficiency of our method through its application to the extraction of capacitances in some representative geometries for IC interconnects

When self-consistency makes a difference

Compound semiconductor power RF and microwave device modeling requires, in many cases, the use of selfconsistent electrothermal equivalent circuits. The slow thermal dynamics and the thermal nonlinearity should be accurately included in the model; otherwise, some response features subtly related to the detailed frequency behavior of the slow thermal dynamics would be inaccurately reproduced or completely distorted. In this contribution we show two examples, concerning current collapse in HBTs and modeling of IMPs in GaN HEMTs. Accurate thermal modeling is proved to be be made compatible with circuit-oriented CAD tools through a proper choice of system-level approximations; in the discussion we exploit a Wiener approach, but of course the strategy should be tailored to the specific problem under consideratio

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Uncertainty quantification for integrated circuits: Stochastic spectral methods

Due to significant manufacturing process variations, the performance of integrated circuits (ICs) has become increasingly uncertain. Such uncertainties must be carefully quantified with efficient stochastic circuit simulators. This paper discusses the recent advances of stochastic spectral circuit simulators based on generalized polynomial chaos (gPC). Such techniques can handle both Gaussian and non-Gaussian random parameters, showing remarkable speedup over Monte Carlo for circuits with a small or medium number of parameters. We focus on the recently developed stochastic testing and the application of conventional stochastic Galerkin and stochastic collocation schemes to nonlinear circuit problems. The uncertainty quantification algorithms for static, transient and periodic steady-state simulations are presented along with some practical simulation results. Some open problems in this field are discussed.MIT Masdar Program (196F/002/707/102f/70/9374

3D Capacitance Extraction With the Method of Moments

In this thesis, the Method of Moments has been applied to calculate capacitance between two arbitrary 3D metal conductors or a capacitance matrix for a 3D multi-conductor system. Capacitance extraction has found extensive use for systems involving sets of long par- allel transmission lines in multi-dielectric environment as well as integrated circuit package including three-dimensional conductors located on parallel planes. This paper starts by reviewing fundamental aspects of transient electro-magnetics followed by the governing dif- ferential and integral equations to motivate the application of numerical methods as Method of Moments(MoM), Finite Element Method(FEM), etc. Among these numerical tools, the surface-based integral-equation methodology - MoM is ideally suited to address the prob- lem. It leads to a well-conditioned system with reduced size, as compared to volumetric methods. In this dissertation, the MoM Surface Integral Equation (SIE)-based modeling approach is developed to realize electrostatic capacitance extraction for 3D geometry. MAT- LAB is employed to validate its e?ciency and e?ectiveness along with design of a friendly GUI. As a base example, a parallel-plate capacitor is considered. We evaluate the accu- racy of the method by comparison with FEM simulations as well as the corresponding quasi-analytical solution. We apply this method to the parallel-plate square capacitor and demonstrate how far could the undergraduate result 0C = A ? =d\u27 be from reality. For the completion of the solver, the same method is applied to the calculation of line capacitance for two- and multi-conductor 2D transmission lines