Monolayer Doping for Fabrication of Recessed Channel MOSFETs

Scaling of semiconductor devices has become a challenge with respect to the design, device performance, reliability, integration and fabrication schemes. For over sixty-years now, from the first design of transistor various challenges has been overcome with various integration schemes to shrink the device whilst increasing the device performance. As the devices are shrinking, there is a need to achieve shallow junctions for better performance of non-planar structures such as FinFETs and 3D FETs. The implementation of conventional doping technique ion-implantation can be a hindering process for the shallow junctions as they tend to damage the crystal due to bombardment of high energy beams. Monolayer doping can be an alternative doping technique as the chemicals react with the semiconductor surface enabling a self-assembled and self-limiting process. MLD exploits the surface reaction properties of the crystalline semiconductors to form covalently bonded, self-assembled dopant molecular monolayers on the semiconductor surface with high doping concentrations. Monolayer doping is implemented to fabricate Recessed Channel MOSFETs which are successful in suppressing the short channel effects by having the channel engineered by implementing the recessed channel grooves which have the potential of reducing the corner barrier effect in comparison to a standard classical planar MOSFET. The subthreshold slope of a 10 µm planar NMOSFET previously fabricated at R.I.T was 150mV/dec, whereas for a 10 µm recessed channel MOSFET fabricated in this work was 117.65mV/dec. The threshold voltage of the 10 µm planar NMOSFET was -0.3V whereas the threshold voltage of the 10 µm recessed channel MOSFETs was 0.2V. The smallest working Recessed Channel MOSFETs fabricated had a channel length of 1 µm. Various integration schemes can be adopted to further investigate and fabricate recessed channel MOSFETs to show better device performance

Design, simulation, fabrication and characterisation of 4H-SiC trench MOSFETs

For solid-state power devices, there exists need for a material with a higher band gap which will result in a higher critical electric field, improved power efficiency and thermal performance. This has resulted in the use of Silicon Carbide (SiC) as a serious alternative to Silicon for power devices. SiC trench MOSFETs have attracted major attention in recent years because of 1) lower on resistance by eliminating the JFET effect which exists in lateral MOSFETs, 2) higher channel density which lowers the threshold voltage and 3) reduction of the required surface area because of the vertical channel. These advantages allow faster switching speeds and the potential for a higher density of devices leading to more compact modules. This work was focused on fabrication of the first generation of 4H-SiC trench MOSFETs in Warwick University. Two main goals were achieved in this work: a comprehensive understanding of fabrication of trenches in 4H-SiC and fabrication of first generation of 4H-SiC trench MOSFET with mobility as high as 3

Integration of Ferroelectric HfO2 onto a III-V Nanowire Platform

The discovery of ferroelectricity in CMOS-compatible oxides, such as doped hafnium oxide, has opened new possibilities for electronics by reviving the use of ferroelectric implementations on modern technology platforms. This thesis presents the ground-up integration of ferroelectric HfO2 on a thermally sensitive III-V nanowire platform leading to the successful implementation of ferroelectric transistors (FeFETs), tunnel junctions (FTJs), and varactors for mm-wave applications. As ferroelectric HfO2 on III-V semiconductors is a nascent technology, a special emphasis is put on the fundamental integration issues and the various engineering challenges facing the technology.The fabrication of metal-oxide-semiconductor (MOS) capacitors is treated as well as the measurement methods developed to investigate the interfacial quality to the narrow bandgap III-V materials using both electrical and operando synchrotron light source techniques. After optimizing both the films and the top electrode, the gate stack is integrated onto vertical InAs nanowires on Si in order to successfully implement FeFETs. Their performance and reliability can be explained from the deeper physical understanding obtained from the capacitor structures.By introducing an InAs/(In)GaAsSb/GaSb heterostructure in the nanowire, a ferroelectric tunnel field effect transistor (ferro-TFET) is fabricated. Based on the ultra-short effective channel created by the band-to-band tunneling process, the localized potential variations induced by single ultra-scaled ferroelectric domains and individual defects are sensed and investigated. By intentionally introducing a gate-source overlap in the ferro-TFET, a non-volatile reconfigurable single-transistor solution for modulating an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing is implemented.Finally, by fabricating scaled ferroelectric MOS capacitors in the front-end with a dedicated and adopted RF and mm-wave backend-of-line (BEOL) implementation, the ferroelectric behavior is captured at RF and mm-wave frequencies

Optoelectronic devices for power conservation and generation

Energy conservation and generation have become increasingly important in society. Here, we pursue novel transistor technologies based on three-dimensional (3D) FinFETs and two-dimensional (2D) materials to make low power, high speed transistors. We also develop quasi-2D silicon thin film solar cells for power generation. First, a novel approach of doping III-V semiconductors is presented. Oxygen rich silicon oxide (SiO [subscript x], where x > 2) is found to behave as a solid dopant source when deposited on InGaAs, followed by thermal annealing. Oxygen, when diffused into InGaAs, act as n-type dopants where the active carrier concentration reaches up to 1.4 x 10¹⁸ cm³. Besides the simple, CMOS compatible doping technique of solid source doping, another interesting factor is the dopant concentration can be altered by the deposited dopant thickness, which adds an additional control knob therefore allowing enhanced control over the doping process. Thermally induced compressive stress within InGaAs due to the difference in coefficient of thermal expansion (CTE) between InGaAs and SiO [subscript x] is known to increase the number of vacancies within InGaAs therefore giving rise to active dopant concentration. This approach can be used to make high speed, low power transistors. Second, study of thin indium metal contacts on InGaAs is presented. Unlike silicon, III-V compound semiconductors such as InGaAs decomposes around 450 ˚C which result in out-diffusion of indium and gallium and decrease in metal-InGaAs contact resistance. By adding a thin layer of indium between the metal-InGaAs interface, the out-diffusion of gallium was minimized. Third, solar cells based on graphene-silicon (GS) heterojunction architecture are demonstrated on bendable crystalline silicon substrates. Flexible, thin silicon films are fabricated by using the thermal expansion difference between electroplated nickel and bulk silicon, which generates residual strain upon thermal cycling. By controlling the amount of thermal stress, silicon thicknesses between 8 and 35 µm are exfoliated through a kerf-less mechanical method. Together with multi-layer graphene (MLG) grown by chemical vapor deposition (CVD) and atomic layer deposition (ALD) of Al₂O₃ as a silicon passivation layer, power conversion efficiencies (PCE) of 7.4 % were achieved on bendable silicon substrates. Finally, Chapter 7 summarizes the all the chapters from this dissertation and some thoughts for future work.Electrical and Computer Engineerin

Moving towards high carrier mobility power devices in silicon and silicon carbide

This thesis reports on recent progress regarding the characterization, design and fabrication of modern power semiconductor devices in Silicon (Si) as well as in the promising wide band gap material Silicon Carbide (SiC). Up to now, state of the art power devices are architectured on the basis of monocrystalline Si-wafers. This is due to the high material quality of Si in combination with the availability of a mature and reliable fabrication technology based on a well-established process library. However, more and more sophisticated device designs such as e.g. the Super-Junction (SJ) architecture require an increasing number of fabrication steps therefore increasing the amount of possible sources of error. Further, more complex three-dimensional dopant distribution profiles are needed for the devices to withstand the high blocking voltage demands of current power semiconductor applications when operated in reverse direction. This dopant distribution has to be monitored, at least for control samples, after implantation, after further thermal processes and during the duty cycle. To ensure reliable device operation, in particular for charge compensated devices, this monitoring or mapping has to be performed locally with high precision and sensitivity. In this work complementary Scanning Probe Microscopy (SPM) based methods like: Kelvin Probe Force Microscopy (KPFM), Scanning Capacitance Force Microscopy (SCFM) and Scanning Spreading Resistance Microscopy (SSRM) have been explored for a precise monitoring of carrier concentration profiles. This is due to the fact that so far none of the established industrial techniques such as e.g. Secondary Ion Mass Spectrometry (SIMS) or Spreading Resistance Probe (SRP) was mature enough to simultaneously full-fill all the major requirements of the semiconductor industry in terms of spatial resolution, sensitivity, reproducibility and the ability to quantify dopant concentrations. Further, SIMS is probing the chemical composition rather than the charge carrier distribution. To ‘look inside’ the inhomogeneously doped sample, smooth device cross-sections need to be prepared in a reliable manner and without distorting the ‘as implanted/activated’ dopant profile. In this way artefacts arising from a topographic signal can be ruled out. For Si the easiest way would be to cleave the wafer along a certain crystallographic direction. However, since the SPM methods presented here shall serve as a characterization tool with a general validity another approach that is also suitable for different crystal structures and materials with a hardness close to diamond had to be found. For this reason a chemical mechanical polishing (CMP) procedure had been developed at PSI. This process was optimized for maintaining a low surface state density as it is important to avoid a complete pinning of the Fermi level for the KPFM measurements. The subsequent Atomic Force Microscopy (AFM) imaging has been performed in collaboration with the experts in the research group of Prof. Ernst Meyer at the University of Basel. Within this project it has been demonstrated that every SPM derived method is capable to qualitatively map carrier concentrations down to an unprecedented low regime. However, a difference regarding the lateral resolution was observed which can be understood by different information depths depending on the underlying physical quantity to be measured together with an imperfect surface preparation which is leading to an accumulation or depletion of defects at the surface. The most critical technique in that sense - due to its high surface sensitivity - is the contact potential difference measurement that is utilized by KPFM to draw conclusions on the carrier concentration. By laser illumination of the sample during the KPFM experiment a Surface Photo Voltage (SPV) occurs in a surface near layer with a thickness in the order of the minority carrier diffusion length. Thus, the surface sensitivity is reduced and the signal distortion due to the unfavourable influence of surface defects gets less pronounced. Even though SCFM is also based on the detection of the electrostatic force that develops between the tip and the sample, this method is less affected by the surface because it is probing a different physical quantity, namely the total capacitance of the rather extended oxide/depletion layer capacitance system. Furthermore, the magnitude of the SCFM signal scales inverse proportionally with respect to the carrier concentration, hence this method is theoretically offering the highest sensitivity in the low concentration regime. Nevertheless, a quantification scheme for this technique is still in development and further work on locally acquired spectroscopic capacitance-voltage (C-V ) measurements is needed towards a reliable quantification procedure. The third SPM derived method SSRM, is operated in contact mode under high normal forces to ensure that the spreading resistance is the dominant resistance contribution for the current flowing between the tip and the sample. Under these circumstances the local carrier concentration and its impact on the magnitude and the sign of the output current can be investigated in a very accurate and quantitative manner. Beside that, the high mechanical forces cause an abrasive motion of the tip while scanning the sample. This feature is beneficial in two ways: on one hand the native oxide and the underlying defect-rich surface layer are removed while on the other hand a phase transformation of a tiny sample volume just below the tip occurs which locally decreases the resistivity and increases the spatial resolution. Hence, the SSRM technique is showing a high degree of reproducibility and is therefore ideal for quantitative studies. As mentioned above the considerable complexity of the fabrication process and the limited material properties of Si in terms of a high critical electric field and a high thermal conductivity accelerated the search for novel substrates for power semiconductor applications. Beside offering an order of magnitude higher critical electric field due to its wide band gap (WBG), SiC also attracted attention since it can be thermally oxidized resulting in a silicon dioxide (SiO2) layer as its native oxide. Therefore, this material has been classified as most promising and theoretical improvements of a - by a factor of 400 - lower ON-resistance have been calculated. However, to date SiC devices are facing other problems related to the engineering of dopant profiles and the more complex nature of the oxidation process which limit their performance and hinder their large-scale commercialization. The incorporation of a specific dopant distribution in SiC is most effectively done by an ion implantation process followed by a high temperature annealing step which is needed to restore the crystal structure after implantation-induced damage and to electronically activate the dopant atoms. This is caused by the fact that in SiC due to its wide band gap of 2.4-3.2 eV (depending on its poly-type) basically no dopant diffusion at reasonable thermal budgets occurs. Notably, not all of these dopant atoms are ionized and contribute to the electric conduction within the semiconductor. Especially the hole concentration p and the acceptor concentration NA can differ significantly in SiC due to the large ionization energies. Hence it has to be taken into account that the final performance of a SiC power device might be inferior to the expected performance from the implantation parameters. This behaviour is in clear contrast to Si where at room temperature basically all donor and acceptor atoms are ionized and no further differentiation between the dopant and the carrier (electronically active dopant) profile has to be made. The above mentioned SPM methods are sensitive to the carrier rather than to the dopant profile and within this work it has been demonstrated that e.g. the p-doped guard ring structure of a SiC Schottky diode which is shielding the metal contact from high electric fields that occur under reverse bias operation can be resolved. Another challenge for SiC Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are low carrier mobilities inside the thin conducting channel at the semiconductor/oxide interface and threshold voltage instabilities. Due to the more complex nature of the oxidation process which requires the removal of carbon atoms in the form of CO or CO2 from the SiC crystal the SiC/SiO2 interface is showing a high density of interface trap states that act as scattering centres and degrade the carrier mobility. Hence, experimentally observed charge carrier mobilities are by a factor of 10 below the theoretical value of the bulk material. Thereby the ON-resistance which is inverse proportional to the mobility is increased which is leading to a higher amount of power dissipation in the ON-state of the device. Unsurprisingly, a lot of research effort has been triggered in this direction resulting in breakthrough called post-oxidation annealing (POA) under gaseous ambients. Nitrogen and phosphorous based chemistries have shown a passivating effect on the density of interface trap states. However, the origin of this mechanism is not yet fully understood. A possible explanation is a counter-doping effect within a thin layer at the semiconductor surface. A second - maybe easier - pathway to increase the channel mobility is the utilization of the crystal anisotropy. The mobility strongly depends on the orientation of the channel with respect to the crystallographic axis. Among them the 1120 direction exhibits the highest mobility. In the here presented project this approach has been utilized to improve the device performance without changing too many parameters regarding the oxidation or post-oxidation treatments at the same time. In this case the remaining challenge was to develop an etching process which is able to etch several um deep trenches into SiC and to precisely control the shape of the resulting trench profile. It has been demonstrated that sharp corners that would cause field crowding at the edges can be eliminated by the usage of very small DC biases applied between the electrode of the plasma chamber and the substrate. Furthermore, the steepness of the sidewalls could be controlled by the composition of the plasma gas flows. Contrary to previous reports we found that the addition of oxygen to the dry etching process is not helping to avoid microtrenching. Either a pure SF6 based process or an SF6 based process with the addition of Ar have shown the best results. With this success a full manufacturing cycle for a nanoscale trench MOSFET has been designed

Non-Silicon MOSFETs and Circuits with Atomic Layer Deposited Higher-k Dielectrics

The quest for technologies beyond 14nm node complementary metal-oxide-semiconductor (CMOS) devices has now called for research on higher-k gate dielectrics integration with high mobility channel materials such as III-V semiconductors and germanium. Ternary oxides, such as La2-xYxO3 and LaAlO3, have been considered as strong candidates due to their high dielectric constants and good thermal stability. Meanwhile, the unique abilities of delivering large area uniform thin film, excellent controlling of composition and thickness to an atomic level, which are keys to ultra-scaled devices, have made atomic layer deposition (ALD) technique an excellent choice. In this thesis, we systematically study the atomic layer epitaxy (ALE) process realized by ALD, ALE higher-k dielectric integration, GaAs nMOSFETs and pMOSFETs on (111)A substrates, and their related CMOS digital logic gate circuits as well as ring oscillators. A record high drain current of 376 mA/mm and a small SS of 74 mV/dec are obtained from planar GaAs nMOSFETs with 1μm gate length. La2-xYxO3/GaAs(111)A interfaces are systematically investigated in both material and electrical aspects. The work has expanded the near 50 years GaAs MOSFETs research to an unprecedented level. Following the GaAs work, Ge n- and p-MOSFETs with epitaxial interfaces are also fabricated and studied. Beyond the conventional semiconductors, the complex oxide channel material SrTiO3 is also explored. Well-behaved LaAlO3/SrTiO3 nMOSFETs with a conducting channel at insulating ALD amorphous LaAlO3 - insulating crystalline SrTiO3 interface are also demonstrated

Schottky source/drain transistor integrated with high-k and metal gate for sub-tenth nm technology

Ph.DDOCTOR OF PHILOSOPH

Contact and source/drain engineering for advanced III-V field-effect transistors

Ph.DDOCTOR OF PHILOSOPH

Wide Bandgap Based Devices: Design, Fabrication and Applications, Volume II

Wide bandgap (WBG) semiconductors are becoming a key enabling technology for several strategic fields, including power electronics, illumination, and sensors. This reprint collects the 23 papers covering the full spectrum of the above applications and providing contributions from the on-going research at different levels, from materials to devices and from circuits to systems