Self-catalyzed and catalyst-free III-V semiconductor nanowire grown by CBE

In this thesis, the growth dynamics and mechanisms of III-V semiconductor nanowires (NWs) and their heterostructures are studied. III-V NWs are realized by self-catalyzed and catalyst-free growth methods on Si (111) substrates by means of chemical beam epitaxy. The Au-free growth approach is particularly important for the integration of III-V semiconductors on silicon toward a CMOS-compatible electronics. The morphological and structural properties of the grown NWs are investigated by scanning (SEM) and transmission electron microscopy (TEM). These NWs exhibit very high aspect ratio and good material quality, which makes them useful to be employed for fundamental studies as well as for application in electronics and optoelectronics. The first part of the thesis is focused on the growth of InAs/InP/GaAsSb core-dual-shell (CDS) NWs. Detailed morphological, structural, and compositional analyses of the NWs as a function of growth parameters are carried out by SEM, TEM, and by energy-dispersive X-ray spectroscopy. Furthermore, by combining the scanning transmission electron microscopy-Moir\ue9 technique with geometric phase analysis, we studied the residual strain and the relaxation mechanisms in this system. We found that InP shell facets are well-developed along the crystallographic <110> and <112> directions only when the nominal thickness is above 1 nm, suggesting an island-growth mode. Moreover, the crystallographic analysis indicates that both InP and GaAsSb shells grow almost coherently to the InAs core along the \u27e8112\u27e9 direction and elastically compressed along the \u27e8110\u27e9 direction. For an InP shell thickness above 8 nm, some dislocations and roughening occur at the interface. This study provides useful general guidelines for the fabrication of high-quality devices based on these CDS NWs. Indeed, we investigated the tunnel coupling between the outer p-type GaAsSb shell and the n-type InAs core in InAs/InP/GaAsSb CDS NWs. Low-temperature (4.2 K) transport measurements in the shell-shell configuration in CDS NWs with 5 nm-thick InP barrier reveal a weak negative differential resistance. Differently, when the InP barrier thickness is increased to 10 nm, this negative differential resistance is fully quenched. The electrical resistance between the InAs core and the GaAsSb shell, measured in core-shell configuration, is significantly higher with respect to the resistance of the InAs core and of the GaAsSb shell. The field effect, applied via a back-gate, has an opposite impact on the electrical transport in the core and in the shell portions. Our results show that electron and hole free carriers populate the InAs and GaAsSb regions respectively and indicate InAs/InP/GaAsSb CDS NWs as an ideal system for the investigation of the physics of interacting electrons and holes at the nanoscale. The second part of this thesis is dedicated to the growth of self-catalyzed InAs/InSb axial heterostructures. The growth mechanisms of these heterostructures are thoroughly investigated as a function of the In and Sb line pressures, and growth time. Some interesting phenomena are observed and analysed. In particular, the presence of an In droplet on top of the InSb segment is shown to be essential to form axial heterostructures in the self-catalyzed vapor-liquid-solid mode. Axial versus radial growth rates of InSb segments are investigated under different growth conditions and described within a dedicated model containing no free parameters. It is shown that a widening of the InSb segment with respect to the InAs stem is caused by the vapor-solid growth on the nanowire sidewalls rather than by the droplet swelling. The In droplet can even shrink smaller than the nanowire facet under Sb-rich conditions. The third part of the thesis is focused on the realization of self-catalyzed InSb quantum dot (QD) embedded into InAs NW. A systematic study on the influence of the growth parameters on the morphology of such NWs is performed. Radial and axial growth rates are studied as a function of growth parameters in order to realize InSb QD NW with controlled morphology. In particular, we have explored different growth conditions to minimize the InAs shell around the InSb QD. We found that the shell thickness around the InSb QD decreases with increasing growth temperature while it increases with an increase of the As line pressure. Furthermore, from the high resolution-TEM analysis, we observed that InAs-stem and InAs-top segment have a wurtzite (WZ) crystal structure with several defects such as stacking faults and twins perpendicular to the growth direction. It is commonly observed that the InAs NWs grown by catalyst-free and self-catalyzed growth methods show highly defective (or mixed WZ/ZB) crystal structure. By contrast, here the InSb QD shows a defect-free zincblende (ZB) crystal structure without any stacking faults, consistently with the energetically preferred cubic structure of the InSb crystals generally attributed to the low ionicity of group III to Sb bonds. This study gives useful information for the realization of InSb QDs with controlled morphology and optimized quality embedded in InAs NWs in the self-catalyzed regime

Surface Nano-Patterning for the Bottom-Up Growth of III-V Semiconductor Nanowire Ordered Arrays

Ordered arrays of vertically aligned semiconductor nanowires are regarded as promising candidates for the realization of all-dielectric metamaterials, artificial electromagnetic materials, whose properties can be engineered to enable new functions and enhanced device performances with respect to naturally existing materials. In this review we account for the recent progresses in substrate nanopatterning methods, strategies and approaches that overall constitute the preliminary step towards the bottom-up growth of arrays of vertically aligned semiconductor nanowires with a controlled location, size and morphology of each nanowire. While we focus specifically on III-V semiconductor nanowires, several concepts, mechanisms and conclusions reported in the manuscript can be invoked and are valid also for different nanowire materials

III–V Nanowires: Synthesis, Property Manipulations, and Device Applications

III–V semiconductor nanowire (NW) materials possess a combination of fascinating properties, including their tunable direct bandgap, high carrier mobility, excellent mechanical flexibility, and extraordinarily large surface-to-volume ratio, making them superior candidates for next generation electronics, photonics, and sensors, even possibly on flexible substrates. Understanding the synthesis, property manipulation, and device integration of these III–V NW materials is therefore crucial for their practical implementations. In this review, we present a comprehensive overview of the recent development in III–V NWs with the focus on their cost-effective synthesis, corresponding property control, and the relevant low-operating-power device applications. We will first introduce the synthesis methods and growth mechanisms of III–V NWs, emphasizing the low-cost solid-source chemical vapor deposition (SSCVD) technique, and then discuss the physical properties of III–V NWs with special attention on their dependences on several typical factors including the choice of catalysts, NW diameters, surface roughness, and surface decorations. After that, we present several different examples in the area of high-performance photovoltaics and low-power electronic circuit prototypes to further demonstrate the potential applications of these NW materials. Towards the end, we also make some remarks on the progress made and challenges remaining in the III–V NW research field

Fabrication of semiconductor nanowire multifunctional devices

Portable multi-functional devices can play a major role in the new age society embracing internet-of-things (IoT). Being able to perform primary functions such as sensing and secondary functions such as storing information is quite critical when out of connectivity. However, such bespoke devices are almost unheard of as it is very difficult to fabricate it due to several factors such as device architecture, dimension, scalability, and parasitic effects. This work describes the fabrication and characterization of a multi-functional device that acts an ultra-sensitive pressure sensor but is also capable of storing that information for a prolonged period. Both sensitivity and charge storage ability are attributed to the inclusion of one-dimensional (1-D) nanostructures. The alternating crystal phases in the as-grown gold (Au) catalyzed GaAs and self-induced AlGaAs/GaAs nanowires (NWs) were used in our case. This thesis discusses the fabrication, growth, characterization, integration and electrical testing involved to produce the multi-functional device. Bespoke nanowires were grown on a template prepared using a combination of nanosphere (NSL) and nanoimprint lithography (NIL) which provided a reproducible large-area periodic array of growth site at a relatively low cost. The inclusion of these NWs in the polymer helps enhance the relative permittivity of the host polymer by a factor of 40 making it an almost-perfect dielectric for a capacitive pressure sensor. NWs also acted as charge storage nodes allowing to extend the functionality. The technique consists of creating nanoholes in silicon dioxide (SiO2) to expose the silicon Si (111) beneath where self-induced NWs can nucleate, while nanodots deposited onto the Si (111) surface serve as catalyst seeds. For Au-catalysed NWs, a monolayer of self-assembled polystyrene nanospheres (PNS 300 nm) was created on a 2 inch Si wafer by spin coating and later etched for a short time before a very thin Au-catalyst layer was deposited. In turn, for self-induced, PNS monolayer was created onto a SiO2-Si substrate. A longer etch was required to reduce PNS diameter significantly to leave relatively larger spacing where chromium is blanket deposited. PNS were lifted off by sonicating the samples in toluene produce the periodic arrays of nanodots and nanoholes, respectively. The underlying SiO2 was etched further through the nanoholes to uncover the Si below. 200 nm holes and 30-70 nm dots were demonstrated through the bespoke methods. The patterned substrates served as master templates, subsequently copied using polydimethylsiloxane (PDMS) to produce a flexible stamp for nanoimprint lithography. A bi-layer resist lift off process was developed to print the replicated nanodots or nanoholes on large-area substrates onto which GaAs NWs were subsequently grown. GaAs NWs were extracted and mixed in PMMA to produce a composite dielectric which was sandwiched between electrodes to act as a capacitor. An order of magnitude increase in relative permittivity (ϵr) is observed after the addition of the NWs allowing a high signal to noise ratio output on the application of pressure. This is due to the addition of higher permittivity nano-filler in the matrix. Furthermore, it was demonstrated that encapsulated high aspect ratio NWs in a host (polymer in this case) can be integrated in devices to improve existing functionality. Devices were successfully fabricated for pressure sensing and memory using the above described low-cost high-volume process with high sensitivity and large memory window, respectively. This demonstration is one of the first steps in enabling low cost electronics without compromising on performance which is imperative for IoT

Recent advances in the Van der Waals epitaxy growth of III‐V semiconductor nanowires on graphene

The recent discovery of the one‐atom‐thick, two‐dimensional graphene layers with exciting properties including superb optical transparency and high mechanical robustness has stimulated extensive research interest for use as an alternative nanowires (NWs) growth platform for applications in next generation, flexible, stretchable, and printable electronic and optoelectronic devices. When combined with the exceptional capabilities of semiconductor NWs including improved light absorption, reduced optical reflectance, enhanced carrier collection, and fast response, the performance of optoelectronic devices could be significantly improved in novel high‐performance, flexible nanodevices. However, the growth of semiconductor NWs on 2D graphene layers is highly challenging owing to the absence of surface dangling bonds on graphene. Intriguingly, the last decade has witnessed a flurry of research activity on the growth of III‐V semiconductor NWs on graphene. In this review, we highlight the significant advancements that have been made in circumventing this challenge to realize the growth of III‐V semiconductor NWs on graphene. We then summarize the recent progress made in the development of graphene‐based NWs devices including photodetectors and solar cells. Finally, a brief conclusion and outlook of the way forward in the growth of semiconductor NWs on graphene is presented

III–V ternary nanowires on Si substrates: growth, characterization and device applications

Over the past decades, the progress in the growth of materials which can be applied to cutting-edge technologies in the field of electronics, optoelectronics and energy harvesting has been remarkable. Among the various materials, group III–V semiconductors are of particular interest and have been widely investigated due to their excellent optical properties and high carrier mobility. However, the integration of III–V structures as light sources and numerous other optical components on Si, which is the foundation for most optoelectronic and electronic integrated circuits, has been hindered by the large lattice mismatch between these compounds. This mismatch results in substantial amounts of strain and degradation of the performance of the devices. Nanowires (NWs) are unique nanostructures that induce elastic strain relaxation, allowing for the monolithic integration of III–V semiconductors on the cheap and mature Si platform. A technique that ensures flexibility and freedom in the design of NW structures is the growth of ternary III–V NWs, which offer a tuneable frame of optical characteristics, merely by adjusting their nominal composition. In this review, we will focus on the recent progress in the growth of ternary III–V NWs on Si substrates. After analysing the growth mechanisms that are being employed and describing the effect of strain in the NW growth, we will thoroughly inspect the available literature and present the growth methods, characterization and optical measurements of each of the III–V ternary alloys that have been demonstrated. The different properties and special treatments required for each of these material platforms are also discussed. Moreover, we will present the results from the works on device fabrication, including lasers, solar cells, water splitting devices, photodetectors and FETs, where ternary III–V NWs were used as building blocks. Through the current paper, we exhibit the up-to-date state in this field of research and summarize the important accomplishments of the past few years

Indium Antimonide Nanowires: Synthesis and Properties

This article summarizes some of the critical features of pure indium antimonide nanowires (InSb NWs) growth and their potential applications in the industry. In the first section, historical studies on the growth of InSb NWs have been presented, while in the second part, a comprehensive overview of the various synthesis techniques is demonstrated briefly. The major emphasis of current review is vapor phase deposition of NWs by manifold techniques. In addition, author review various protocols and methodologies employed to generate NWs from diverse material systems via self-organized fabrication procedures comprising chemical vapor deposition, annealing in reactive atmosphere, evaporation of InSb, molecular/chemical beam epitaxy, solution-based techniques, and top-down fabrication method. The benefits and ill effects of the gold and self-catalyzed materials for the growth of NWs are explained at length. Afterward, in the next part, four thermodynamic characteristics of NW growth criterion concerning the expansion of NWs, growth velocity, Gibbs-Thomson effect, and growth model were expounded and discussed concisely. Recent progress in device fabrications is explained in the third part, in which the electrical and optical properties of InSb NWs were reviewed by considering the effects of conductivity which are diameter dependent and the applications of NWs in the fabrications of field-effect transistors, quantum devices, thermoelectrics, and detectors

Growth of InAs and Bi1-xSBx nanowires on silicon for nanoelectronics and topological qubits by molecular beam epitaxy

Grâce à leur propriétés uniques, les nanofils d'InAs et de Bi1-xSbx sont important pour les domaines de la nanoélectronique et de l'informatique quantique. Alors que la mobilité électronique de l'InAs est intéressante pour les nanoélectroniques; l'aspect isolant topologique du Bi1-xSbx peut être utilisé pour la réalisation de Qubits basés sur les fermions de Majorana. Dans les deux cas, l'amélioration de la qualité du matériau est obligatoire et ceci est l'objectif principal cette thèse ou` nous étudions l'intégration des nanofils InAs sur silicium (compatibles CMOS) et où nous développons un nouvel isolant topologique nanométrique: le Bi1-xSbx. Pour une compatibilité CMOS complète, la croissance d'InAs sur Silicium nécessite d'être auto- catalysée, entièrement verticale et uniforme sans dépasser la limite thermique de 450 ° C. Ces normes CMOS, combineés à la différence de paramètre de maille entre l'InAs et le silicium, ont empêché l'intégration de nanofils InAs pour les dispositifs nanoélectroniques. Dans cette thèse, deux nouvelles préparations de surface du Si ont été étudiées impliquant des traitements Hydrogène in situ et conduisant à la croissance verticale et auto-catalysée de nanofils InAs compatible avec les limitations CMOS. Les différents mécanismes de croissance résultant de ces préparations de surface sont discutés en détail et un passage du mécanisme Vapor-Solid (VS) au mécanisme Vapor- Liquid-Solid (VLS) est rapporté. Les rapports d'aspect très élevé des nanofils d'InAs sont obtenus en condition VLS: jusqu'à 50 nm de diamètre et 3 microns de longueur. D'autre part, le Bi1-xSbx est le premier isolant topologique 3D confirmé expérimentalement. Dans ces nouveaux matériaux, la présence d'états surfacique conducteurs, entourant le coeur isolant, peut héberger les fermions de Majorana utilisés comme Qubits. Cependant, la composition du Bi1-xSbx doit être comprise entre 0,08 et 0,24 pour que le matériau se comporte comme un isolant topologique. Nous rapportons pour la première fois la croissance de nanofils Bi1-xSbx sans défaut et à composition contrôlée sur Si. Différentes morphologies sont obtenues, y compris des nanofils, des nanorubans et des nanoflakes. Leur diamètre peut être de 20 nm pour plus de 10 microns de long, ce qui en fait des candidats idéaux pour des dispositifs quantiques. Le rôle clé du flux Bi, du flux de Sb et de la température de croissance sur la densité, la composition et la géométrie des structures à l'échelle nanométrique est étudié et discuté en détail.InAs and Bi1-xSbx nanowires with their distinct material properites hold promises for nanoelec- tronics and quantum computing. While the high electron mobility of InAs is interesting for na- noelectronics applications, the 3D topological insulator behaviour of Bi1-xSbx can be used for the realization of Majorana Fermions based qubit devices. In both the cases improving the quality of the nanoscale material is mandatory and is the primary goal of the thesis, where we study CMOS compatible InAs nanowire integration on Silicon and where we develop a new nanoscale topological insulator. For a full CMOS compatiblity, the growth of InAs on Silicon requires to be self-catalyzed, fully vertical and uniform without crossing the thermal budge of 450 °C. These CMOS standards, combined with the high lattice mismatch of InAs with Silicon, prevented the integration of InAs nanowires for nanoelectronics devices. In this thesis, two new surface preparations of the Silicon were studied involving in-situ Hydrogen gas and in-situ Hydrogen plasma treatments and leading to the growth of fully vertical and self-catalyzed InAs nanowires compatible with the CMOS limitations. The different growth mechanisms resulting from these surface preparations are discussed in detail and a switch from Vapor-Solid (VS) to Vapor- Liquid-Solid (VLS) mechanism is reported. Very high aspect ratio InAs nanowires are obtained in VLS condition: upto 50 nm in diameter and 3 microns in length. On the other hand, Bi1-xSbx is the first experimentally confirmed 3D topololgical insulator. In this new material, the presence of robust 2D conducting states, surrounding the 3D insulating bulk can be engineered to host Majorana fermions used as Qubits. However, the compostion of Bi1-xSbx should be in the range of 0.08 to 0.24 for the material to behave as a topological insula- tor. We report growth of defect free and composition controlled Bi1-xSbx nanowires on Si for the first time. Different nanoscale morphologies are obtained including nanowires, nanoribbons and nanoflakes. Their diameter can be 20 nm thick for more than 10 microns in length, making them ideal candidates for quantum devices. The key role of the Bi flux, the Sb flux and the growth tem- perature on the density, the composition and the geometry of nanoscale structures is investigated and discussed in detail

Three-dimensional field-effect transistors with top-down and bottom-up nanowire-array channels

This dissertation research effort explores new transistor topologies using three-dimensional nanowire (NW)-array channels formed by both bottom-up and top-down synthesis. The bottom-up NW research centers on the Au-catalyzed planar GaAs NW assembly discovered at the University of Illinois Urbana-Champaign (UIUC). The top-down NW research approach involves plasma etching of an emerging wide-bandgap material, Gallium Oxide (Ga2O3), to make arrays of NW channels (or fins) for high-power electronics. Bottom-up AlGaAs/GaAs heterostructure core-shell planar NWs are demonstrated on a wafer scale with excellent yield. Their placement is determined by lithographically patterning an array of Au seeds on semi-insulating GaAs substrate. The GaAs NWs assemble by lateral epitaxy via a vapor-liquid-solid mechanism and align in parallel arrays as a result of the (100) GaAs crystal plane orientation; then, a thin-film AlGaAs layer conforms to the GaAs NWs to form AlGaAs/GaAs NW high-electron mobility channels. Radio frequency (RF) transistors are fabricated and show excellent dc and high-frequency performance. An fmax > 75 GHz with 104 is measured which is superior compared to carbon-based nanoelectronics and “spin-on III-V NWs”. A comprehensive small-signal model is used to extract the contributing and limiting factors to the RF performance of AlGaAs/GaAs NW-array transistors and predict future performance. Finally, a process is developed to show that III-V NWs on sacrificial epitaxial templates can be transferred to arbitrary substrates. Top-down NWs were formed from Sn-doped Ga2O3 homoepitaxially grown on semi-insulating beta-phase Ga2O3 substrates by metal-organic vapor phase epitaxy. First, conventional planar transistors were fabricated from a sample set to characterize and understand the electrical performance as a function of Sn-doping and epitaxial channel thickness. Second, the high-critical field strength was evaluated to highlight the benefit of using Ga2O3 as a disruptive technology to GaN and SiC. Lastly, the planar transistor results feed into a design for a top-down NW-array transistor. The Ga2O3 NW-arrays were formed by BCl3 plasma etching. A new wrap-gate transistor demonstrates normally-off (enhancement-mode) operation with a high breakdown voltage exceeding 600 V which is superior to any transistor using a 3D channel