Operational Trans-Resistance Amplifier Based Tunable Wave Active Filter

In this paper, Operational Trans-Resistance Amplifier (OTRA) based wave active filter structures are presented. They are flexible and modular, making them suitable to implement higher order filters. The circuits implement the resistors using matched transistors, operating in linear region, making them well suited for IC fabrication. They are insensitive to parasitic input capacitances and input resistances due to the internally grounded input terminals of OTRA. As an application, a doubly terminated third order Butterworth low pass filter has been implemented, by substituting OTRA based wave equivalents of passive elements. PSPICE simulations are given to verify the theoretical analysis

Computer-Aided Design of Switched-Capacitor Filters

This thesis describes a series of computer methods for the design of switched-capacitor filters. Current software is greatly restricted in the types of transfer function that can be designed and in the range of filter structures by which they can be implemented. To solve the former problem, several new filter approximation algorithms are derived from Newton's method, yielding the Remez algortithm as a special case (confirming its convergency properties). Amplitude responses with arbitrary passband shaping and stopband notch positions are computed. Points of a specified degree of tangency to attenuation boundaries (touch points) can be placed in the response, whereby a family of transfer functions between Butterworth and elliptic can be derived, offering a continuous trade-off in group delay and passive sensitivity properties. The approximation algorithms have also been applied to arbitrary group delay correction by all-pass functions. Touch points form a direct link to an iterative passive ladder design method, which bypasses the need for Hurwitz factorisation. The combination of iterative and classical synthesis methods is suggested as the best compromise between accuracy and speed. It is shown that passive ladder prototypes of a minimum-node form can be efficiently simulated by SC networks without additional op-amps. A special technique is introduced for canonic realisation of SC ladder networks from transfer functions with finite transmission at high frequency, solving instability and synthesis difficulties. SC ladder structures are further simplified by synthesising the zeros at +/-2fs which are introduced into the transfer function by bilinear transformation. They cause cancellation of feedthrough branches and yield simplified LDI-type SC filter structures, although based solely on the bilinear transform. Matrix methods are used to design the SC filter simulations. They are shown to be a very convenient and flexible vehicle for computer processing of the linear equations involved in analogue filter design. A wide variety of filter structures can be expressed in a unified form. Scaling and analysis can readily be performed on the system matrices with great efficiency. Finally, the techniques are assembled in a filter compiler for SC filters called PANDDA. The application of the above techniques to practical design problems is then examined. Exact correction of sinc(x), LDI termination error, pre-filter and local loop telephone line weightings are illustrated. An optimisation algorithm is described, which uses the arbitrary passband weighting to predistort the transfer function for response distortions. Compensation of finite amplifier gain-bandwidth and switch resistance effects in SC filters is demonstrated. Two commercial filter specifications which pose major difficulties for traditional design methods are chosen as examples to illustrate PANDDA's full capabilities. Significant reductions in order and total area are achieved. Finally, test results of several SC filters designed using PANDDA for a dual-channel speech-processing ASIC are presented. The speed with which high-quality, standard SC filters can be produced is thus proven

Analogue filter networks: developments in theory, design and analyses

Not availabl

Realization of Integrable Low- Voltage Companding Filters for Portable System Applications

Undoubtedly, today’s integrated electronic systems owe their remarkable performance primarily to the rapid advancements of digital technology since 1970s. The various important advantages of digital circuits are: its abstraction from the physical details of the actual circuit implementation, its comparative insensitiveness to variations in the manufacturing process, and the operating conditions besides allowing functional complexity that would not be possible using analog technology. As a result, digital circuits usually offer a more robust behaviour than their analog counterparts, though often with area, power and speed drawbacks. Due to these and other benefits, analog functionality has increasingly been replaced by digital implementations. In spite of the advantages discussed above, analog components are far from obsolete and continue to be key components of modern electronic systems. There is a definite trend toward persistent and ubiquitous use of analog electronic circuits in day-to-day life. Portable electronic gadgets, wireless communications and the widespread application of RF tags are just a few examples of contemporary developments. While all of these electronic systems are based on digital circuitry, they heavily rely on analog components as interfaces to the real world. In fact, many modern designs combine powerful digital systems and complementary analog components on a single chip for cost and reliability reasons. Unfortunately, the design of such systems-on-chip (SOC) suffers from the vastly different design styles of analog and digital components. While mature synthesis tools are readily available for digital designs, there is hardly any such support for analog designers apart from wellestablished PSPICE-like circuit simulators. Consequently, though the analog part usually occupies only a small fraction of the entire die area of an SOC, but its design often constitutes a major bottleneck within the entire development process. Integrated continuous-time active filters are the class of continuous-time or analog circuits which are used in various applications like channel selection in radios, anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a filter is the dynamic range; this is the ratio of the largest to the smallest signal that can be applied at the input of the filter while maintaining certain specified performance. The dynamic range required in the filter varies with the application and is decided by the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the capacitor area of an integrated active filter increases in proportion to its dynamic range. This situation is incompatible with the needs of integrated systems, especially battery operated ones. In addition to this fundamental dependence of power dissipation on dynamic range, the design of integrated active filters is further complicated by the reduction of supply voltage of integrated circuits imposed by the scaling down of technologies to attain twin objective of higher speed and lower power consumption in digital circuits. The reduction in power consumption with decreasing supply voltage does not apply to analog circuits. In fact, considerable innovation is required with a reduced supply voltage even to avoid increasing power consumption for a given signal to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer. A technique which has attracted the attention of circuit designers as a possible route to filters with higher dynamic range per unit power consumption is “companding”. Companding (compression-expansion) filters are a very promising subclass of continuous-time analog filters, where the input (linear) signal is initially compressed before it will be handled by the core (non-linear) system. In order to preserve the linear operation of the whole system, the non-linear signal produced by the core system is converted back to a linear output signal by employing an appropriate output stage. The required compression and expansion operations are performed by employing bipolar transistors in active region or MOS transistors in weak inversion; the systems thus derived are known as logarithmic-domain (logdomain) systems. In case MOS transistors operated in saturation region are employed, the derived structures are known as Square-root domain systems. Finally, the third class of companding filters can also be obtained by employing bipolar transistors in active region or MOS transistors in weak inversion; the derived systems are known as Sinh-domain systems. During the last several years, a significant research effort has been already carried out in the area of companding circuits. This is due to the fact that their main advantages are the capability for operation in low-voltage environment and large dynamic range originated from their companding nature, electronic tunability of the frequency characteristics, absence of resistors and the potential for operations in varied frequency regions.Thus, it is obvious that companding filters can be employed for implementing high-performance analog signal processing in diverse frequency ranges. For example, companding filters could be used for realizing subsystems in: xDSL modems, disk drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked loops, FM stereo demodulator, touch-tone telephone tone decoder and crossover network used in a three-way high-fidelity loudspeaker etc. A number of design methods for companding filters and their building blocks have been introduced in the literature. Most of the proposed filter structures operate either above 1.5V or under symmetrical (1.5V) power supplies. According to data that provides information about the near future of semiconductor technology, International Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of analog integrated circuits is the usage of low-voltage building blocks that use a single 0.5-1.5V power supply. Therefore, the present investigation was primarily concerned with the study and design of low voltage and low power Companding filters. The work includes the study about: the building blocks required in implementing low voltage and low power Companding filters; the techniques used to realize low voltage and low power Companding filters and their various areas of application. Various novel low voltage and low power Companding filter designs have been developed and studied for their characteristics to be applied in a particular portable area of application. The developed designs include the N-th order universal Companding filter designs, which have been reported first time in the open literature. Further, an endeavor has been made to design Companding filters with orthogonal tuning of performance parameters so that the designs can be simultaneously used for various features. The salient features of each of the developed circuit are described. Electronic tunability is one of the major features of all of the designs. Use of grounded capacitors and resistorless designs in all the cases makes the designs suitable for IC technology. All the designs operate in a low-voltage and low-power environment essential for portable system applications. Unless specified otherwise, all the investigations on these designs are based on the PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The performance of each circuit has been validated by comparing the characteristics obtained using simulation with the results present in the open literature. The proposed designs could not be realized in silicon due to non-availability of foundry facility at the place of study. An effort has already been started to realize some of the designs in silicon and check their applicability in practical circuits. At the basic level, one of the proposed Companding filter designs was implemented using the commercially available transistor array ICs (LM3046N) and was found to verify the theoretical predictions obtained from the simulation results

Modern VLSI Analogue Filter Design: Methodology and Software Development

This thesis describes various approaches for the design of modern analogue filters and provides a practical filter and equaliser design aids system XFILT. The thesis begins by placing the analogue filter design technique and software into a historical and technology perspective. The evolution of the analogue filter is traced from early work, through the passive-RLC to transconductor-C and switched-current realisations. The software development in VLSI analogue filter automation is reviewed. For SC filter design, a cascade SC design approach which includes a novel pole-zero pairing method and a comprehensive comparison of SC filter realisation using different biquads are presented. Very useful guidelines for the choice of a suitable biquad structure according to the nature of the filter problem are presented. The canonical realisations of SC filter are studied. The multirate SC system design is described. Several strategies and the algorithms for multirate SC system design are proposed. In transconductor-C filter design research, the definition of a canonical ladder based transconductor-C filter is introduced, and two canonical ladder based transconductor-C filter design approaches are proposed. The ladder based transconductor-C equaliser design is also discussed. A practical video frequency transconductor-C filter and equaliser design is given to demonstrate the utility of the matrix design method and the design software. A new approach to realise exact ladder based SI filter with first and second generation memory cell has been proposed. The bilinear transformation is used in the design procedure. Eight different SI ladder based structures can be obtained for one prototype ladder. Therefore it provides SI filter designers with various circuit choices based on different requirement such as area, maximum ratio of transistor aspect ratio limit, sensitivity or noise performance. Techniques to improve dynamic range and reduce circuit parameter spread are also presented. The proposed approach is well suited for a computer compiler implementation. A suitability study of each decomposition method for different filtering applications is also carried out and a general guideline for the choice of different decomposition methods is obtained. A comparison study on SI filter sensitivity performance based on first generation and second generation memory cells is carried out. Using four filter examples, it is demonstrated that SI filters based on a second generation SI memory cell have good sensitivity performance. For SI filters based on first generation memory cells, it is shown that a high ratio of clock frequency to cutoff frequency in the lowpass case, or a high ratio of clock frequency to midband frequency in the bandpass case would introduce high sensitivity. A novel approach for SI ladder filter based on the S2I integrator is also proposed and a canonical realisation for SI filter based on S2I integrator is developed. Examination of SI equaliser design reveals that cascade structure is a better candidate than ladder based structure. Multirate SI filter system design is also studied. Finally, a very brief introduction to the assembly of the design methods in this thesis into a software package XHLT for VLSI analogue filter and equaliser design is given. The user aspects of XFILT have been discussed and various capabilities of XFILT are demonstrated. Several advanced facilities which remove traditional design limitations are illustrated. The philosophy of the system is explained. It is shown that the distinguished features of XFILT are Ease of Use. General Applicability, and Ease of Extension. The system structure is described and the graphics interface which acts both as user friendly interface and a system manager of all the software is outlined. Fabricated SC, transconductor-C, and SI filter and equaliser have been designed by using XFILT. The system is under further enhancement toward a commercial product

Switched-current filtering systems: design, synthesis and software development

Allpass filters are commonly employed in many applications to perform group delay equalisation in the passband. They are non-minimum phase by definition and are characterised by poles and zeros in mirror-image symmetry. SI allpass filters of both cascade biquad and bilinear-LDI ladder types have been in existence. These were implemented using Euler based integrators. Cascade biquads are known to have highly sensitive amplitude responses and Euler integrators suffer from excess phase. The equalisers that are proposed here are based on bilinear integrators instead of Euler ones. Derivation of these equalisers can proceed from either the s-domain, or directly from the z-domain, where a prototype is synthesised using the respective continued-fractions expansions, and simulated using standard matrix methods. The amplitude response of the bilinear allpass filter is shown to be completely insensitive to deviations in the reactive ladder section. Simulations of sensitivities and non-ideal responses reveal the advantages and disadvantages of the various structures. Existing DI multirate filters have to date been implemented as direct-form FIR and IIR polyphase structures, or as simple cascade biquad or ladder structures with non-optimum settling times. FIR structures require a large number of impulse coefficients to realise highly selective responses. Even in the case of linear phase response with symmetric impulse coefficients, when the number of coefficients can be halved, significant overheads can be incurred by additional multiplexing circuitry. Direct-form IIR structures are simple but are known to be sensitive to coefficient deviations and structures with non-optimum settling times operate entirely at the higher clock frequency. The novel SI decimators and interpolators proposed are based on low sensitivity ladder structures coupled with FIR polyphase networks. They operate entirely at the lower clock frequency which maximises the time available for the memory cells to settle. Two different coupling architectures with different advantages and disadvantages are studied

Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation

This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power

Switched-capacitor filters and their application in data communications

There have been considerable developments in the field of switched-capacitor filter design over the past decade. Those developments which allow the operating frequency range of switched-capacitor filters to be extended are considered. The solution to the approximation and synthesis problems for l.d.i.-based switched-capacitor ladder filters discovered by Scanlan is explained. Computer software which implements his technique for low-pass filters is presented. A number of techniques for synthesising the network are investigated. It is shown that numerical difficulties limit the order of filter which can be synthesised. The sensitivity properties of switched-capacitor ladder filters are explored. A technique, which has been implemented in software, for evaluating the amplitude sensitivity of such filters is described. This program is used to demonstrate that the frequency variable terminations in the equivalent circuit of the switched-capacitor ladder filter adversely affect its sensitivity properties. Grcuit topologies which result in improved high frequency performance are considered, and a fully differential filter structure for high frequency operation is proposed. Circuits are presented for a digitally programmable switched-capacitor line equaliser and optimisation techniques for its design are investigated. The extension of the design to incorporate adaptive operation is discussed, and circuits based on the above designs which have been fabricated at the National Micro-electronics Research Centre (N.M.R.C.) in Cork are described