FPGA based synchronous multi-channel PWM generator for humanoid robot

In this paper, synchronous multi-channel pulse width modulation (PWM) generator for driving servo motors of humanoid robot was proposed. In an application, the humanoid robot requires smooth and beautiful movement, therefore the PWM signal for each servo motor must be synchronized. Since microcontroller (slave) has no enough channels to generate synchronous PWMs for 32 servo motors, field programmable gate array (FPGA) was used as slave for the humanoid robot. The FPGA was controlled by microcontroller (master) using serial communication. Simulation results show the system can perform serial communication, synchronize, and convert data well. The system can also generate PWM simultaneously with accurate duty cycle and fix period of 20ms

An Event-Based Synchronization Framework for Controller Hardware-in-the-loop Simulation of Electric Railway Power Electronics Systems

The Controller Hardware_in_the_loop (CHIL) simulation is gaining popularity as a cost_effective, efficient, and reliable tool in the design and development process of fast_growing electrified transportation power converters. However, it is challenging to implement the conventional CHIL simulations on the railway power converters with complex topologies and high switching frequencies due to strict real_time constraints. Therefore, this paper proposes an event-based synchronization CHIL (ES_CHIL) framework for high_fidelity simulation of these electrified railway power converters. Different from conventional CHIL simulations synchronized through the time axis, the ES_CHIL framework is synchronized through the event axis. Therefore, it can ease the real_time constraint and broaden the upper bound on the system size and switching frequency. Besides, models and algorithms with higher accuracy, such as the diode model with natural commutation processes, can be used in the ES-CHIL framework. The proposed framework is validated for a 350 kW wireless power transformer system containing 24 fully controlled devices and 36 diodes by comparing it with Simulink and physical experiments. This research improves the fidelity and application range of the power converters CHIL simulation. Thus, it helps to accelerate the prototype design and performance evaluation process for electrified railways and other applications with such complex converters

Programmable mixed-signal circuits

A novel concept for programmable mixed-signal circuits is presented based on programmable transmission gates. For implementation, memristively switching devices are suggested as the most promising candidates for realization of fast and small-footprint signal routing switches with small resistance and capacity. As a proof-of-concept, LT Spice simulations of digital and analogue example circuits implemented by the new concept are demonstrated. It is discussed how important design parameters can be tuned in the circuity. Compared to competing technologies such as Field Programmable Analogue Arrays or Application-Specific Integrated Circuits, the presented concept allows for development of ultra-flexible, reconfigurable, and cheap embedded mixed-signal circuits for applications where only limited space is available or high bandwidth is required

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the well-known AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management

Integration of Digital Signal Processing Block in SymbiFlow FPGA Toolchain for Artix-7 Devices

The open-source community is a valuable resource for many hobbyists and researchers interested in collaborating and contributing towards publicly available tools. In the area of field programmable gate arrays (FPGAs) this is no exception. Contributors seek to reverse-engineer the functions of large proprietary FPGA devices. An interesting challenge for open-source FPGA engineers has been reverse-engineering the operation and bitstreams of digital signal processing (DSP) blocks located in FPGAs. SymbiFlow is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. For SymbiFlow, mapping logical multipliers to DSP blocks and generating DSP block bitstreams has been left unimplemented for the Artix-7 family of FPGAs. This research seeks to rectify this shortcoming by introducing DSP information for the place and route functions into SymbiFlow. By delving into the SymbiFlow architecture definitions and creating functioning FPGA assembly code (FASM) files for Project X-Ray, a bitstream generator for Artix-7, we have been able to determine the desired output of the open-source Versatile Place & Route tool that will generate a working DSP bitstream. We diagnose and implement changes needed throughout the SymbiFlow toolchain, allowing for DSP design bitstreams to be successfully generated with open-source tools

Alternativas de implementación de un controlador digital en FPGA para un convertidor Buck en prácticas de laboratorio

El conocimiento de nuevas técnicas por parte de los estudiantes y futuros ingenieros es fundamental para que puedan desenvolverse de una manera más cómoda y eficiente en su futuro como diseñadores hardware. La presentación de las nuevas técnicas y recursos durante la fase de estudios son clave para abordar este planteamiento. Este trabajo se centra en la exploración de alternativas actuales de implementación para un controlador en VHDL. Se trata de explorar nuevas opciones y recursos actuales que las nuevas herramientas de desarrollo incorporan para facilitar el trabajo al diseñador. Como base se han tenido en cuenta varios artículos de investigación, elaborados por profesores de la escuela, en los que estas alternativas habían sido planteadas. Para la realización del trabajo se ha utilizado la implementación del control de un convertidor electrónico de potencia Buck. Este controlador, que será implementado sobre una FPGA, ha sido diseñado de varias maneras. Primero, se ha utilizado la técnica tradicional con el planteamiento de las operaciones coma fija. Con ayuda de librerías de coma fija y coma flotante se han desarrollado versiones adicionales. Gracias a los bloques IP de coma flotante se ha realizado una alternativa a la librería float. Por último, se ha implementado el controlador en un microcontrolador que puede ser embebido dentro de la FPGA, haciendo posible la programación de las operaciones utilizando código C

Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices

Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation community where a significant need exists. This dissertation presents a new self-healing digital I&C architecture called BioSymPLe, inspired from the way nature responds, defends and heals: the stem cells in the immune system of living organisms, the life cycle of the living cell, and the pathway from Deoxyribonucleic acid (DNA) to protein. The BioSymPLe architecture is integrating biological concepts, fault tolerance techniques, and operational schematics for the international standard IEC 61131-3 to facilitate adoption in the automation industry. BioSymPLe is organized into three hierarchical levels: the local function migration layer from the top side, the critical service layer in the middle, and the global function migration layer from the bottom side. The local layer is used to monitor the correct execution of functions at the cellular level and to activate healing mechanisms at the critical service level. The critical layer is allocating a group of functional B cells which represent the building block that executes the intended functionality of critical application based on the expression for DNA genetic codes stored inside each cell. The global layer uses a concept of embryonic stem cells by differentiating these type of cells to repair the faulty T cells and supervising all repair mechanisms. Finally, two industrial applications have been mapped on the proposed architecture, which are capable of tolerating a significant number of faults (transient, permanent, and hardware common cause failures CCFs) that can stem from environmental disturbances and we believe the nexus of its concepts can positively impact the next generation of critical systems in the automation industry

三相電圧形インバータ用モデル予測制御のFPGAによる実装手法の開発： モデルベース設計手法，HILシミュレーション，FPGAリソース最適化

Model predictive control (MPC), a modern switching control method, has gained considerable interest in performing control objectives of power converters. One of the categories in a wide family of MPC is finite control set-MPC (FCS-MPC) that utilizes the discrete-time model of a power converter having a limited number of switching states for solving the optimization problem online. In FCS-MPC, a discrete-time model of the power converter is used to predict future values of control parameters and an optimization function (cost function) is used to select the optimized switching state of the converter. High computational requirements of the FCS-MPC is a concern for the system implementation. Field-programmable gate array (FPGA) is an effective alternative to handle the computational burden of the control algorithm because of its parallel processing nature. In general, the MPC algorithm is performed through a programming approach either for DSP or FPGA. However, digital resource utilization is another concern for the development and real-time system implementation. Digital resource optimization requires a high value of in-depth knowledge to write the hardware descriptive code. Moreover, debugging is also a tedious and time-consuming task that is not appropriate for the development and analysis of the controller as well as prototyping. In this work, the implementation of FCS-MPC is performed by adopting the modelling approach in a digital simulator that provides a virtual FPGA environment for system development. In addition, hardware-in-the-loop (HIL) technique is used for testing of controller performance before experimental validation. The current prediction is a core part of the FCS-MPC and a coefficient used for the current prediction that is computed using the system parameters affects the controller performance. In this work, a novel approach is presented to update the predictive model, called an adaptive predictive model, corresponding to a change in the load resistance while keeping a fixed value of load inductance. The fixed, approximated and adaptive values of a coefficient are adopted for current prediction to investigate the behaviour of the controller. The performance of the FCS-MPC depends on the sampling frequency used for the discretization of the converter model that governs the switching frequency of the converter. The performance can be improved with higher sampling frequency, however, resulting in higher switching frequency that ultimately increases the switching losses in the power devices. Apart from that, a non-zero steady-state error is one of the concerns of the FCS-MPC implementation. In general, dedicated constraints for the reduction in average switching frequency and SSE are incorporated inside a cost function in conventional FCS-MPC. Nevertheless, that ultimately increases the computational burden. A modified cost function based on a novel constraint is proposed for the improvement in SSE as well as a reduction in the switching frequency using the modified FCS-MPC approach. To validate the performance of the proposed constraint, a comparative analysis is presented with the constraint of a change in switching state considering indices SSE as well as average switching frequency. Moreover, the different load currents and sampling time are considered to evaluate SSE considering similar load current ripples. To evaluate the robustness of the FCS-MPC algorithms, a step-change in reference current is considered for the demonstration of dynamic performance. Moreover, an analytical approach based implementation strategies is proposed for FPGA resource optimization of the FCS-MPC development in a digital simulator for the FPGA-based system implementation. The implementation of FCS-MPC in stationary αβ and rotating dq frames is adopted for in-depth system analysis. The implementation strategies are compared based on FPGA resource requirements for the FCS-MPC in both frames corresponding to the fixed, approximated and adaptive coefficient values of the predictive model. The optimum design based controller model is used for the FPGA-based experimental system implementation. Xilinx system generator (XSG) as a digital simulator that is an integrated platform with MATLAB/Simulink is used for the development of the controller. The FCS-MPC is implemented for the load-side current control of a three-phase voltage source inverter (VSI) system. A Xilinx FPGA board (Zedboard Zynq Evaluation and Development Kit) is used for the HIL simulation as well as the real-time system implementation.九州工業大学博士学位論文 学位記番号：生工博甲第367号 学位授与年月日：令和2年3月25日1: INTRODUCTION| 2: FINITE CONTROL SET - MODEL PREDICTIVE CONTROL| 3: MODEL-BASED DESIGN AND HIL SIMULATION| 4: ADVANCED FCS?MPC: ADAPTIVE PREDICTIVE MODEL AND MODIFIED COST FUNCTION| 5: FPGA RESOURCE OPTIMIZATION| 6: CONCLUSIONS AND FUTURE WORK九州工業大学令和元年