Enhancing Digital Controllability in Wideband RF Transceiver Front-Ends for FTTx Applications

Enhancing the digital controllability of wideband RF transceiver front-ends helps in widening the range of operating conditions and applications in which such systems can be employed. Technology limitations and design challenges often constrain the extensive adoption of digital controllability in RF front-ends. This work focuses on three major aspects associated with the design and implementation of a digitally controllable RF transceiver front-end for enhanced digital control. Firstly, the influence of the choice of semiconductor technology for a system-on-chip integration of digital gain control circuits are investigated. The digital control of gain is achieved by utilizing step attenuators that consist of cascaded switched attenuation stages. A design methodology is presented to evaluate the influence of the chosen technology on the performance of the three conventionally used switched attenuator topologies for desired attenuation levels, and the constraints that the technology suitable for high amplification places on the attenuator performance are examined. Secondly, a novel approach to the integrated implementation of gain slope equalization is presented, and the suitability of the proposed approach for integration within the RF front-end is verified. Thirdly, a sensitivity-aware implementation of a peak power detector is presented. The increased employment of digital gain control also increases the requirements on the sensitivity of the power detector employed for adaptive power and gain control. The design, implementation, and measurement results of a state-of-the-art wideband power detector with high sensitivity and large dynamic range are presented. The design is optimized to provide a large offset cancellation range, and the influence of offset cancellation circuits on the sensitivity of the power detector is studied. Moreover, design considerations for high sensitivity performance of the power detector are investigated, and the noise contributions from individual sub-circuits are evaluated. Finally, a wideband RF transceiver front-end is realized using a commercially available SiGe BiCMOS technology to demonstrate the enhancements in the digital controllability of the system. The RF front-end has a bandwidth of 500 MHz to 2.5 GHz, an input dynamic range of 20 dB, a digital gain control range larger than 30 dB, a digital gain slope equalization range from 1.49 dB/GHz to 3.78 dB/GHz, and employs a power detector with a sensitivity of -56 dBm and dynamic range of 64 dB. The digital control in the RF front-end is implemented using an on-chip serial-parallel-interface (SPI) that is controlled by an external micro-controller. A prototype implementation of the RF front-end system is presented as part of an RFIC intended for use in optical transceiver modules for fiber-to-the-x applications

A Self-Calibrated Power Detector and Current Sensor for Use in a Power Amplifier Control Circuit

The power amplifier in a transmitter, especially high-power transmitters, generally uses more power than any other component in the signal chain. As a result, large power savings can be achieved if the efficiency of the power amplifier is optimized. Additionally, power amplifiers in high-power transmitters generally experience substantial amounts of reliability-reducing stress such as high temperature operation. Given these considerations, a power amplifier control loop is proposed which will calculate various parameters of the amplifier, such as the power-added efficiency. This control loop will then adjust the input power and DC bias current of the power amplifier to maximize the efficiency while also ensuing the amplifier is not placed in a situation where its reliability is compromised. This thesis will discuss the design of two major blocks that are required in this control loop: a DC bias current sensor and a power detector. The DC bias current sensor must accurately measure the DC bias of the power amplifier since this current is used to calculate the DC power dissipation for the power-added efficiency. In order to ensure the DC current sensor’s output is accurate over a wide temperature range, a reference current calibration scheme is introduced. The fabricated current sensor is able to achieve a measurement accuracy of +/-1% over a current range from 100mA to 4A. The power detector must measure the input and output power of the power amplifier since the power added efficiency takes into account the gain of the amplifier. The proposed power detector utilizes an on-chip reference generator in order to calibrate the peak detector used and provide an accurate and absolute power level. The simulated power detector is able to provide an accuracy of +/-0.5dB over a dynamic range of 40dB. These two designs will be incorporated in the overall power amplifier control system in future work

MOSFET dynamic thermal sensor for IC testing applications

This paper analyses how a single metal-oxide-semiconductor field-effect transistor (MOSFET) can be employed as a thermal sensor to measure on-chip dynamic thermal signals caused by a power-dissipating circuit under test (CUT). The measurement is subjected to two low-pass filters (LPF). The first LPF depends on the thermal properties of the heat-conduction medium (i.e. silicon) and the CUT-sensor distance, whereas the second depends on the electrical properties of the sensing circuit such as the bias current and the dimensions of the MOSFET sensor. This is evaluated along the paper through theoretical models, simulations, and experimental data resulting from a chip fabricated in 0.35 mu m CMOS technology. Finally, the proposed thermal sensor and the knowledge extracted from this paper are applied to estimate the linearity of a radio-frequency (RF) amplifier. (C) 2016 Elsevier B.V. All rights reserved.Peer ReviewedPostprint (author's final draft

Synthesis of Translinear Analog Signal Processing Systems

Even in the predominantly digital world of today, analog circuits maintain a significant and necessary role in the way electronic signals are generated and processed. A straightforward method for synthesizing analog circuits would greatly improve the way that analog circuits are currently designed. In this dissertation, I build upon a synthesis methodology for translinear circuits originally introduced by Bradley Minch that uses multiple-input translinear elements (MITEs) as its fundamental building block. Introducing a graphical representation for the way that MITEs are connected, the designer can get a feel for how the equations relate to the physical circuit structure and allows for a visual method for reducing the number of transistors in the final circuit. Having refined some of the synthesis steps, I illustrate the methodology with many examples of static and dynamic MITE networks. For static MITE networks, I present a squaring reciprocal circuit and two versions of a vector magnitude circuit. A first-order log-domain filter and an RMS-to-DC converter are synthesized showing two first-order systems, both linear and non-linear. Higher order systems are illustrated with the synthesis of a second-order log-domain filter and a quadrature oscillator. The resulting circuits from several of these examples are combined to form a phase-locked loop (PLL). I present simulated and experimental results from many of these examples. Additionally, I present information related to the process of programming the floating-gate charge for the MITEs through the use of Fowler-Nordheim tunneling and hot-electron injection. I also include code for a Perl program that determines the optimum connections to minimize the total number of MITEs for a given circuit.NSF Career award CCR-998462

Single-MOSFET DC thermal sensor for RF-amplifier central frequency extraction

© 2017 Elsevier B.V. A DC thermal sensor based on a single metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed to extract high-frequency electrical features of embedded circuits. The MOSFET sensor is monolithically integrated with the circuit under test (CUT) and then monitors by thermal means the DC power dissipated by the CUT, which carries high-frequency electrical information. After explaining the theory behind this testing approach, the paper demonstrates the feasibility of the proposed MOSFET sensor through simulations and experiments. These are carried out using a radio-frequency (RF) power amplifier as a CUT and thermally extracting its central frequency (440 MHz). The MOSFET sensor results are assessed using an infrared camera as a reference. The main advantage of the proposed sensing method is that the impact on the integrated circuit (IC) layout area is minimum, which is crucial when testing RF-ICs. Moreover, in comparison with previous works, the cost and complexity of the required instrumentation is lower.Postprint (author's final draft

CMOS Hyperbolic Sine ELIN filters for low/audio frequency biomedical applications

Hyperbolic-Sine (Sinh) filters form a subclass of Externally-Linear-Internally-Non- Linear (ELIN) systems. They can handle large-signals in a low power environment under half the capacitor area required by the more popular ELIN Log-domain filters. Their inherent class-AB nature stems from the odd property of the sinh function at the heart of their companding operation. Despite this early realisation, the Sinh filtering paradigm has not attracted the interest it deserves to date probably due to its mathematical and circuit-level complexity. This Thesis presents an overview of the CMOS weak inversion Sinh filtering paradigm and explains how biomedical systems of low- to audio-frequency range could benefit from it. Its dual scope is to: consolidate the theory behind the synthesis and design of high order Sinh continuous–time filters and more importantly to confirm their micro-power consumption and 100+ dB of DR through measured results presented for the first time. Novel high order Sinh topologies are designed by means of a systematic mathematical framework introduced. They employ a recently proposed CMOS Sinh integrator comprising only p-type devices in its translinear loops. The performance of the high order topologies is evaluated both solely and in comparison with their Log domain counterparts. A 5th order Sinh Chebyshev low pass filter is compared head-to-head with a corresponding and also novel Log domain class-AB topology, confirming that Sinh filters constitute a solution of equally high DR (100+ dB) with half the capacitor area at the expense of higher complexity and power consumption. The theoretical findings are validated by means of measured results from an 8th order notch filter for 50/60Hz noise fabricated in a 0.35μm CMOS technology. Measured results confirm a DR of 102dB, a moderate SNR of ~60dB and 74μW power consumption from 2V power supply

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

Output Power and Gain Monitoring in RF CMOS Class A Power Amplifiers by Thermal Imaging

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The viability of using off-chip single-shot imaging techniques for local thermal testing in integrated Radio Frequency (RF) power amplifiers (PA’s) is analyzed. With this approach, the frequency response of the output power and power gain of a Class A RF PA is measured, also deriving information about the intrinsic operation of its transistors. To carry out this case study, the PA is heterodynally driven, and its electrical behavior is down converted into a lower frequency thermal field acquirable with an InfraRed Lock-In Thermography (IR-LIT) system. After discussing the theory, the feasibility of the proposed approach is demonstrated and assessed with thermal sensors monolithically integrated in the PA. As crucial advantages to RF-testing, this local approach is noninvasive and demands less complex instrumentation than the mainstream commercially available solutions.Peer ReviewedPostprint (author's final draft

An Analog VLSI Deep Machine Learning Implementation

Machine learning systems provide automated data processing and see a wide range of applications. Direct processing of raw high-dimensional data such as images and video by machine learning systems is impractical both due to prohibitive power consumption and the “curse of dimensionality,” which makes learning tasks exponentially more difficult as dimension increases. Deep machine learning (DML) mimics the hierarchical presentation of information in the human brain to achieve robust automated feature extraction, reducing the dimension of such data. However, the computational complexity of DML systems limits large-scale implementations in standard digital computers. Custom analog signal processing (ASP) can yield much higher energy efficiency than digital signal processing (DSP), presenting means of overcoming these limitations. The purpose of this work is to develop an analog implementation of DML system. First, an analog memory is proposed as an essential component of the learning systems. It uses the charge trapped on the floating gate to store analog value in a non-volatile way. The memory is compatible with standard digital CMOS process and allows random-accessible bi-directional updates without the need for on-chip charge pump or high voltage switch. Second, architecture and circuits are developed to realize an online k-means clustering algorithm in analog signal processing. It achieves automatic recognition of underlying data pattern and online extraction of data statistical parameters. This unsupervised learning system constitutes the computation node in the deep machine learning hierarchy. Third, a 3-layer, 7-node analog deep machine learning engine is designed featuring online unsupervised trainability and non-volatile floating-gate analog storage. It utilizes massively parallel reconfigurable current-mode analog architecture to realize efficient computation. And algorithm-level feedback is leveraged to provide robustness to circuit imperfections in analog signal processing. At a processing speed of 8300 input vectors per second, it achieves 1×1012 operation per second per Watt of peak energy efficiency. In addition, an ultra-low-power tunable bump circuit is presented to provide similarity measures in analog signal processing. It incorporates a novel wide-input-range tunable pseudo-differential transconductor. The circuit demonstrates tunability of bump center, width and height with a power consumption significantly lower than previous works