Dynamic selection and estimation of the digital predistorter parameters for power amplifier linearization

© © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient's update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the original basis functions defining the DPD in the forward path are orthonormalized for DPD adaptation in the feedback path by means of a precalculated principal component analysis (PCA) transformation. The robustness and reliability of the precalculated PCA transformation (i.e., PCA transformation matrix obtained off line and only once) is tested and verified. Then, at the second step, a properly modified partial least squares (PLS) method, named dynamic partial least squares (DPLS), is applied to obtain the minimum and most relevant transformed components required for updating the coefficients of the DPD linearizer. The combination of the PCA transformation with the DPLS extraction of components is equivalent to a canonical correlation analysis (CCA) updating solution, which is optimum in the sense of generating components with maximum correlation (instead of maximum covariance as in the case of the DPLS extraction alone). The proposed dynamic extraction technique is evaluated and compared in terms of computational cost and performance with the commonly used QR decomposition approach for solving the least squares (LS) problem. Experimental results show that the proposed method (i.e., combining PCA with DPLS) drastically reduces the amount of DPD coefficients to be estimated while maintaining the same linearization performance.Peer ReviewedPostprint (author's final draft

ワイヤレス通信のための先進的な信号処理技術を用いた非線形補償法の研究

The inherit nonlinearity in analogue front-ends of transmitters and receivers have had primary impact on the overall performance of the wireless communication systems, as it gives arise of substantial distortion when transmitting and processing signals with such circuits. Therefore, the nonlinear compensation (linearization) techniques become essential to suppress the distortion to an acceptable extent in order to ensure sufficient low bit error rate. Furthermore, the increasing demands on higher data rate and ubiquitous interoperability between various multi-coverage protocols are two of the most important features of the contemporary communication system. The former demand pushes the communication system to use wider bandwidth and the latter one brings up severe coexistence problems. Having fully considered the problems raised above, the work in this Ph.D. thesis carries out extensive researches on the nonlinear compensations utilizing advanced digital signal processing techniques. The motivation behind this is to push more processing tasks to the digital domain, as it can potentially cut down the bill of materials (BOM) costs paid for the off-chip devices and reduce practical implementation difficulties. The work here is carried out using three approaches: numerical analysis & computer simulations; experimental tests using commercial instruments; actual implementation with FPGA. The primary contributions for this thesis are summarized as the following three points: 1) An adaptive digital predistortion (DPD) with fast convergence rate and low complexity for multi-carrier GSM system is presented. Albeit a legacy system, the GSM, however, has a very strict requirement on the out-of-band emission, thus it represents a much more difficult hurdle for DPD application. It is successfully implemented in an FPGA without using any other auxiliary processor. A simplified multiplier-free NLMS algorithm, especially suitable for FPGA implementation, for fast adapting the LUT is proposed. Many design methodologies and practical implementation issues are discussed in details. Experimental results have shown that the DPD performed robustly when it is involved in the multichannel transmitter. 2) The next generation system (5G) will unquestionably use wider bandwidth to support higher throughput, which poses stringent needs for using high-speed data converters. Herein the analog-to-digital converter (ADC) tends to be the most expensive single device in the whole transmitter/receiver systems. Therefore, conventional DPD utilizing high-speed ADC becomes unaffordable, especially for small base stations (micro, pico and femto). A digital predistortion technique utilizing spectral extrapolation is proposed in this thesis, wherein with band-limited feedback signal, the requirement on ADC speed can be significantly released. Experimental results have validated the feasibility of the proposed technique for coping with band-limited feedback signal. It has been shown that adequate linearization performance can be achieved even if the acquisition bandwidth is less than the original signal bandwidth. The experimental results obtained by using LTE-Advanced signal of 320 MHz bandwidth are quite satisfactory, and to the authors’ knowledge, this is the first high-performance wideband DPD ever been reported. 3) To address the predicament that mobile operators do not have enough contiguous usable bandwidth, carrier aggregation (CA) technique is developed and imported into 4G LTE-Advanced. This pushes the utilization of concurrent dual-band transmitter/receiver, which reduces the hardware expense by using a single front-end. Compensation techniques for the respective concurrent dual-band transmitter and receiver front-ends are proposed to combat the inter-band modulation distortion, and simultaneously reduce the distortion for the both lower-side band and upper-side band signals.電気通信大学201

A General Approach to Fully Linearize the Power Amplifiers in mMIMO with Less Complexity

A radio frequency (RF) power amplifier (PA) plays an important role to amplify the message signal at higher power to transmit it to a distant receiver. Due to a typical nonlinear behavior of the PA at high power transmission, a digital predistortion (DPD), exploiting the preinversion of the nonlinearity, is used to linearize the PA. However, in a massive MIMO (mMIMO) transmitter, a single DPD is not sufficient to fully linearize the hundreds of PAs. Further, for the full linearization, assigning a separate DPD to each PA is complex and not economical. In this work, we address these challenges via the proposed low-complexity DPD (LC-DPD) scheme. Initially, we describe the fully-featured DPD (FF-DPD) scheme to linearize the multiple PAs and examine its complexity. Thereafter, using it, we derive the LC-DPD scheme that can adaptively linearize the PAs as per the requirement. The coefficients in the two schemes are learned using the algorithms that adopt indirect learning architecture based recursive prediction error method (ILA-RPEM) due to its adaptive and free from matrix inversion operations. Furthermore, for the LC-DPD structure, we have proposed three algorithms based on correlation of its common coefficients with the distinct coefficients. Lastly, the performance of the algorithms are quantified using the obtained numerical results

Contribution to dimensionality reduction of digital predistorter behavioral models for RF power amplifier linearization

The power efficiency and linearity of radio frequency (RF) power amplifiers (PAs) are critical in wireless communication systems. The main scope of PA designers is to build the RF PAs capable to maintain high efficiency and linearity figures simultaneously. However, these figures are inherently conflicted to each other and system-level solutions based on linearization techniques are required. Digital predistortion (DPD) linearization has become the most widely used solution to mitigate the efficiency versus linearity trade-off. The dimensionality of the DPD model depends on the complexity of the system. It increases significantly in high efficient amplification architectures when considering current wideband and spectrally efficient technologies. Overparametrization may lead to an ill-conditioned least squares (LS) estimation of the DPD coefficients, which is usually solved by employing regularization techniques. However, in order to both reduce the computational complexity and avoid ill-conditioning problems derived from overparametrization, several efforts have been dedicated to investigate dimensionality reduction techniques to reduce the order of the DPD model. This dissertation contributes to the dimensionality reduction of DPD linearizers for RF PAs with emphasis on the identification and adaptation subsystem. In particular, several dynamic model order reduction approaches based on feature extraction techniques are proposed. Thus, the minimum number of relevant DPD coefficients are dynamically selected and estimated in the DPD adaptation subsystem. The number of DPD coefficients is reduced, ensuring a well-conditioned LS estimation while demanding minimum hardware resources. The presented dynamic linearization approaches are evaluated and compared through experimental validation with an envelope tracking PA and a class-J PA The experimental results show similar linearization performance than the conventional LS solution but at lower computational cost.La eficiencia energetica y la linealidad de los amplificadores de potencia (PA) de radiofrecuencia (RF) son fundamentales en los sistemas de comunicacion inalambrica. El principal objetivo a alcanzar en el diserio de amplificadores de radiofrecuencia es lograr simultaneamente elevadas cifras de eficiencia y de linealidad. Sin embargo, estas cifras estan inherentemente en conflicto entre si, y se requieren soluciones a nivel de sistema basadas en tecnicas de linealizacion. La linealizacion mediante predistorsion digital (DPD) se ha convertido en la solucion mas utilizada para mitigar el compromise entre eficiencia y linealidad. La dimension del modelo del predistorsionador DPD depende de la complejidad del sistema, y aumenta significativamente en las arquitecturas de amplificacion de alta eficiencia cuando se consideran los actuales anchos de banda y las tecnologfas espectralmente eficientes. El exceso de parametrizacion puede conducir a una estimacion de los coeficientes DPD, mediante minimos cuadrados (LS), mal condicionada, lo cual generalmente se resuelve empleando tecnicas de regularizacion. Sin embargo, con el fin de reducir la complejidad computacional y evitar dichos problemas de mal acondicionamiento derivados de la sobreparametrizacion, se han dedicado varies esfuerzos para investigar tecnicas de reduccion de dimensionalidad que permitan reducir el orden del modelo del DPD. Esta tesis doctoral contribuye a aportar soluciones para la reduccion de la dimension de los linealizadores DPD para RF PA, centrandose en el subsistema de identificacion y adaptacion. En concrete, se proponen varies enfoques de reduccion de orden del modelo dinamico, basados en tecnicas de extraccion de caracteristicas. El numero minimo de coeficientes DPD relevantes se seleccionan y estiman dinamicamente en el subsistema de adaptacion del DPD, y de este modo la cantidad de coeficientes DPD se reduce, lo cual ademas garantiza una estimacion de LS bien condicionada al tiempo que exige menos recursos de hardware. Las propuestas de linealizacion dinamica presentados en esta tesis se evaluan y comparan mediante validacion experimental con un PA de seguimiento de envolvente y un PA tipo clase J. Los resultados experimentales muestran unos resultados de linealizacion de los PA similares a los obtenidos cuando se em plea la solucion LS convencional, pero con un coste computacional mas reducido.Postprint (published version

Sparse identification of volterra models for power amplifiers without pseudoinverse computation

Article number 9178996We present a new formulation of the doubly orthogonal matching pursuit (DOMP) algorithm for the sparse recovery of Volterra series models. The proposal works over the covariance matrices by taking advantage of the orthogonal properties of the solution at each iteration and avoids the calculation of the pseudoinverse matrix to obtain the model coefficients. A detailed formulation of the algorithm is provided along with a computational complexity assessment, showing a fixed complexity per iteration compared with its previous versions in which it depends on the iteration number. Moreover, we empirically demonstrate the reduction in computational complexity in terms of runtime and highlight the pruning capabilities through its application to the digital predistortion of a class J power amplifier operating under 5G-NR signals with the bandwidth of 20 and 30 MHz, concluding that this proposal significantly outperforms existing techniques in terms of computational complexity

A fast engineering approach to high efficiency power amplifier linearization for avionics applications

This PhD thesis provides a fast engineering approach to the design of digital predistortion (DPD) linearizers from several perspectives: i) enhancing the off-line training performance of open-loop DPD, ii) providing robustness and reducing the computational complexity of the parameters identification subsystem and, iii) importing machine learning techniques to favor the automatic tuning of power amplifiers (PAs) and DPD linearizers with several free-parameters to maximize power efficiency while meeting the linearity specifications. One of the essential parts of unmanned aerial vehicles (UAV) is the avionics, being the radio control one of the earliest avionics present in the UAV. Unlike the control signal, for transferring user data (such as images, video, etc.) real-time from the drone to the ground station, large transmission rates are required. The PA is a key element in the transmitter chain to guarantee the data transmission (video, photo, etc.) over a long range from the ground station. The more linear output power, the better the coverage or alternatively, with the same coverage, better SNR allows the use of high-order modulation schemes and thus higher transmission rates are achieved. In the context of UAV wireless communications, the power consumption, size and weight of the payload is of significant importance. Therefore, the PA design has to take into account the compromise among bandwidth, output power, linearity and power efficiency (very critical in battery-supplied devices). The PA can be designed to maximize its power efficiency or its linearity, but not both. Therefore, a way to deal with this inherent trade-off is to design high efficient amplification topologies and let the PA linearizers take care of the linearity requirements. Among the linearizers, DPD linearization is the preferred solution to both academia and industry, for its high flexibility and linearization performance. In order to save as many computational and power resources as possible, the implementation of an open-loop DPD results a very attractive solution for UAV applications. This thesis contributes to the PA linearization, especially on off-line training for open-loop DPD, by presenting two different methods for reducing the design and operating costs of an open-loop DPD, based on the analysis of the DPD function. The first method focuses on the input domain analysis, proposing mesh-selecting (MeS) methods to accurately select the proper samples for a computationally efficient DPD parameter estimation. Focusing in the MeS method with better performance, the memory I-Q MeS method is combined with feature extraction dimensionality reduction technique to allow a computational complexity reduction in the identification subsystem by a factor of 65, in comparison to using the classical QR-LS solver and consecutive samples selection. In addition, the memory I-Q MeS method has been proved to be of crucial interest when training artificial neural networks (ANN) for DPD purposes, by significantly reducing the ANN training time. The second method involves the use of machine learning techniques in the DPD design procedure to enlarge the capacity of the DPD algorithm when considering a high number of free parameters to tune. On the one hand, the adaLIPO global optimization algorithm is used to find the best parameter configuration of a generalized memory polynomial behavioral model for DPD. On the other hand, a methodology to conduct a global optimization search is proposed to find the optimum values of a set of key circuit and system level parameters, that properly combined with DPD linearization and crest factor reduction techniques, can exploit at best dual-input PAs in terms of maximizing power efficiency along wide bandwidths while being compliant with the linearity specifications. The advantages of these proposed techniques have been validated through experimental tests and the obtained results are analyzed and discussed along this thesis.Aquesta tesi doctoral proporciona unes pautes per al disseny de linealitzadors basats en predistorsió digital (DPD) des de diverses perspectives: i) millorar el rendiment del DPD en llaç obert, ii) proporcionar robustesa i reduir la complexitat computacional del subsistema d'identificació de paràmetres i, iii) incorporació de tècniques d'aprenentatge automàtic per afavorir l'auto-ajustament d'amplificadors de potència (PAs) i linealitzadors DPD amb diversos graus de llibertat per poder maximitzar l’eficiència energètica i al mateix temps acomplir amb les especificacions de linealitat. Una de les parts essencials dels vehicles aeris no tripulats (UAV) _es l’aviònica, sent el radiocontrol un dels primers sistemes presents als UAV. Per transferir dades d'usuari (com ara imatges, vídeo, etc.) en temps real des del dron a l’estació terrestre, es requereixen taxes de transmissió grans. El PA _es un element clau de la cadena del transmissor per poder garantir la transmissió de dades a grans distàncies de l’estació terrestre. A major potència de sortida, més cobertura o, alternativament, amb la mateixa cobertura, millor relació senyal-soroll (SNR) la qual cosa permet l’ús d'esquemes de modulació d'ordres superiors i, per tant, aconseguir velocitats de transmissió més altes. En el context de les comunicacions sense fils en UAVs, el consum de potència, la mida i el pes de la càrrega útil són de vital importància. Per tant, el disseny del PA ha de tenir en compte el compromís entre ample de banda, potència de sortida, linealitat i eficiència energètica (molt crític en dispositius alimentats amb bateries). El PA es pot dissenyar per maximitzar la seva eficiència energètica o la seva linealitat, però no totes dues. Per tant, per afrontar aquest compromís s'utilitzen topologies amplificadores d'alta eficiència i es deixa que el linealitzador s'encarregui de garantir els nivells necessaris de linealitat. Entre els linealitzadors, la linealització DPD és la solució preferida tant per al món acadèmic com per a la indústria, per la seva alta flexibilitat i rendiment. Per tal d'estalviar tant recursos computacionals com consum de potència, la implementació d'un DPD en lla_c obert resulta una solució molt atractiva per a les aplicacions UAV. Aquesta tesi contribueix a la linealització del PA, especialment a l'entrenament fora de línia de linealitzadors DPD en llaç obert, presentant dos mètodes diferents per reduir el cost computacional i augmentar la fiabilitat dels DPDs en llaç obert. El primer mètode se centra en l’anàlisi de l’estadística del senyal d'entrada, proposant mètodes de selecció de malla (MeS) per seleccionar les mostres més significatives per a una estimació computacionalment eficient dels paràmetres del DPD. El mètode proposat IQ MeS amb memòria es pot combinar amb tècniques de reducció del model del DPD i d'aquesta manera poder aconseguir una reducció de la complexitat computacional en el subsistema d’identificació per un factor de 65, en comparació amb l’ús de l'algoritme clàssic QR-LS i selecció de mostres d'entrenament consecutives. El segon mètode consisteix en l’ús de tècniques d'aprenentatge automàtic pel disseny del DPD quan es considera un gran nombre de graus de llibertat (paràmetres) per sintonitzar. D'una banda, l'algorisme d’optimització global adaLIPO s'utilitza per trobar la millor configuració de paràmetres d'un model polinomial amb memòria generalitzat per a DPD. D'altra banda, es proposa una estratègia per l’optimització global d'un conjunt de paràmetres clau per al disseny a nivell de circuit i sistema, que combinats amb linealització DPD i les tècniques de reducció del factor de cresta, poden maximitzar l’eficiència de PAs d'entrada dual de gran ample de banda, alhora que compleixen les especificacions de linealitat. Els avantatges d'aquestes tècniques proposades s'han validat mitjançant proves experimentals i els resultats obtinguts s'analitzen i es discuteixen al llarg d'aquesta tesi

Independent digital predistortion parameters estimation using adaptive principal component analysis

©2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents an estimation/adaptation method based on the adaptive principal component analysis (APCA) technique to guarantee the identification of the minimum necessary parameters of a digital predistorter. The proposed estimation/adaptation technique is suitable for online field-programmable gate array or system on chip implementation. By exploiting the orthogonality of the resulting transformed matrix obtained with the APCA technique, it is possible to reduce the number of coefficients to be estimated which, at the same time, has a beneficial regularization effect by preventing ill-conditioning or overfitting problems. Therefore, this identification/adaptation method enhances the robustness of the parameter estimation and simplifies the adaptation by reducing the number of estimated coefficients. Due to the orthogonality of the new basis, these parameters can be estimated independently, thus allowing for scalability. Experimental results will show that it is possible to determine the minimum number of parameters to be estimated in order to meet the targeted linearity levels while ensuring a robust well-conditioned identification. Moreover, the results will show how thanks to the orthogonality property of the new basis functions, the coefficients of the digital predistorter can be estimated independently. This allows to tradeoff the digital predistorter adaptation time versus performance and hardware complexity.Peer ReviewedPostprint (author's final draft

Partial least squares identification of multi look-up table digital predistorters for concurrent dual-band envelope tracking power amplifiers

©208 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a technique to estimate the coefficients of a multiple-look-up table (LUT) digital predistortion (DPD) architecture based on the partial least-squares (PLS) regression method. The proposed 3-D distributed memory LUT architecture is suitable for efficient FPGA implementation and compensates for the distortion arising in concurrent dual-band envelope tracking power amplifiers. On the one hand, a new variant of the orthogonal matching pursuit algorithm is proposed to properly select only the best LUTs of the DPD function in the forward path, and thus reduce the number of required coefficients. On the other hand, the PLS regression method is proposed to address both the regularization problem of the coefficient estimation and, at the same time, reducing the number of coefficients to be estimated in the DPD feedback identification path. Moreover, by exploiting the orthogonality of the PLS transformed matrix, the computational complexity of the parameters' identification can be significantly simplified. Experimental results will prove how it is possible to reduce the DPD complexity (i.e., the number of coefficients) in both the forward and feedback paths while meeting the targeted linearity levels.Peer ReviewedPostprint (author's final draft

Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors’ knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.Peer Reviewe