Symmetric rearrangeable networks and algorithms

A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications of these networks are found in the areas of System on Chip (SoC) and Network on Chip (NoC). Deterministic routing algorithms used in NoC applications suffer low scalability and slow execution time. On the other hand, faster algorithms are blocking and thus limit throughput. This will be an acceptable trade-off for many applications where achieving ”wire speed” on the on-chip network would require extensive optimisation of the attached devices. In this thesis I designed an algorithm that has much lower blocking probabilities than other suboptimal algorithms but a much faster execution time than deterministic routing algorithms. The suboptimal method uses the looping algorithm in its outermost stages and then in the two distinct subnetworks deeper in the switch uses a fast but suboptimal path search method to find available paths. The worst case time complexity of this new routing method is O(NlogN) using a single processor, which matches the best known results reported in the literature. Disruption of the ongoing communications in this class of networks during rearrangements is an open issue. In this thesis I explored a modification of the topology of these networks which gives rise to what is termed as repackable networks. A repackable topology allows rearrangements of paths without intermittently losing connectivity by breaking the existing communication paths momentarily. The repackable network structure proposed in this thesis is efficient in its use of hardware when compared to other proposals in the literature. As most of the deterministic algorithms designed for Benes networks implement a permutation of all inputs to find the routing tags for the requested inputoutput pairs, I proposed a new algorithm that can work for partial permutations. If the network load is defined as ρ, the mean number of active inputs in a partial permutation is, m = ρN, where N is the network size. This new method is based on mapping the network stages into a set of sub-matrices and then determines the routing tags for each pair of requests by populating the cells of the sub-matrices without creating a blocking state. Overall the serial time complexity of this method is O(NlogN) and O(mlogN) where all N inputs are active and with m < N active inputs respectively. With minor modification to the serial algorithm this method can be made to work in the parallel domain. The time complexity of this routing algorithm in a parallel machine with N completely connected processors is O(log^2 N). With m active requests the time complexity goes down to (logmlogN), which is better than the O(log^2 m + logN), reported in the literature for 2^0.5((log^2 -4logN)^0.5-logN)<= ρ <= 1. I also designed multistage symmetric rearrangeable networks using larger switching elements and implement a new routing algorithm for these classes of networks. The network topology and routing algorithms presented in this thesis should allow large scale networks of modest cost, with low setup times and moderate blocking rates, to be constructed. Such switching networks will be required to meet the bandwidth requirements of future communication networks

Symmetrical/Asymmetrical Winding Reconfiguration in Multiphase Machines

This paper investigates multiphase drives in which winding configuration (symmetrical or asymmetrical) can be easily obtained by only rearranging voltage source inverter (VSI) power supply cables at the machine’s terminal box. The type of the machines where this is possible is identified and the examples of reconfiguration are given and explained. Following from the examples (for nine- and fifteen-phase cases), a general reconfiguration algorithm is introduced. As shown, changing asymmetrical to symmetrical winding configuration (and vice versa) means that just another mimic diagram needs to be placed over the existing one on the machine’s terminal box. Possible reconfigurations of a six-phase machine, which do not follow the same pattern, are also addressed. Differences caused by different winding configuration are identified and experimentally confirmed using a nine-phase surface mounted permanent magnet synchronous machine (PMSM) and a nine-phase induction machine (IM)

Wavelength reconfigurability for next generation optical access networks

Next generation optical access networks should not only increase the capacity but also be able to redistribute the capacity on the fly in order to manage larger variations in traffic patterns. Wavelength reconfigurability is the instrument to enable such capability of network-wide bandwidth redistribution since it allows dynamic sharing of both wavelengths and timeslots in WDM-TDM optical access networks. However, reconfigurability typically requires tunable lasers and tunable filters at the user side, resulting in cost-prohibitive optical network units (ONU). In this dissertation, I propose a novel concept named cyclic-linked flexibility to address the cost-prohibitive problem. By using the cyclic-linked flexibility, the ONU needs to switch only within a subset of two pre-planned wavelengths, however, the cyclic-linked structure of wavelengths allows free bandwidth to be shifted to any wavelength by a rearrangement process. Rearrangement algorithm are developed to demonstrate that the cyclic-linked flexibility performs close to the fully flexible network in terms of blocking probability, packet delay, and packet loss. Furthermore, the evaluation shows that the rearrangement process has a minimum impact to in-service ONUs. To realize the cyclic-linked flexibility, a family of four physical architectures is proposed. PRO-Access architecture is suitable for new deployments and disruptive upgrades in which the network reach is not longer than 20 km. WCL-Access architecture is suitable for metro-access merger with the reach up to 100 km. PSB-Access architecture is suitable to implement directly on power-splitter-based PON deployments, which allows coexistence with current technologies. The cyclically-linked protection architecture can be used with current and future PON standards when network protection is required

Machine Learning for Multi-Layer Open and Disaggregated Optical Networks

L'abstract è presente nell'allegato / the abstract is in the attachmen

Analogue filter networks: developments in theory, design and analyses

Not availabl

Engineering Education and Research Using MATLAB

MATLAB is a software package used primarily in the field of engineering for signal processing, numerical data analysis, modeling, programming, simulation, and computer graphic visualization. In the last few years, it has become widely accepted as an efficient tool, and, therefore, its use has significantly increased in scientific communities and academic institutions. This book consists of 20 chapters presenting research works using MATLAB tools. Chapters include techniques for programming and developing Graphical User Interfaces (GUIs), dynamic systems, electric machines, signal and image processing, power electronics, mixed signal circuits, genetic programming, digital watermarking, control systems, time-series regression modeling, and artificial neural networks

SIRU development. Volume 1: System development

A complete description of the development and initial evaluation of the Strapdown Inertial Reference Unit (SIRU) system is reported. System development documents the system mechanization with the analytic formulation for fault detection and isolation processing structure; the hardware redundancy design and the individual modularity features; the computational structure and facilities; and the initial subsystem evaluation results