36 research outputs found
First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS
We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth
Advances in Solid State Circuit Technologies
This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields
An IF input continuous-time sigma-delta analog-digital converter with high image rejection.
Shen Jun-Hua.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 151-154).Abstracts in English and Chinese.Abstract --- p.ii摘要 --- p.ivAcknowledgments --- p.viTable of Contents --- p.viiList of Figures --- p.ixList of Tables --- p.xiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1. --- Overview --- p.1Chapter 1.2. --- Motivation and Objectives --- p.5Chapter 1.3. --- Original Contributions of This Work --- p.6Chapter 1.4. --- Organization of the Thesis --- p.7Chapter Chapter 2 --- Sigma-delta Modulation and IF A/D Conversion --- p.8Chapter 2.1. --- Introduction --- p.8Chapter 2.2. --- Fundamentals of Sigma-delta Modulation --- p.9Chapter 2.2.1. --- Feedback Controlled System --- p.9Chapter 2.2.2. --- Quantization Noise --- p.11Chapter 2.2.3. --- Oversampling and Noise-shaping --- p.11Chapter 2.2.4. --- Stability --- p.15Chapter 2.2.5. --- Noise Sources --- p.17Chapter 2.2.6. --- Baseband Sigma-delta Modulation --- p.28Chapter 2.2.7. --- Bandpass Sigma-delta Modulation --- p.28Chapter 2.3. --- Discrete-time Sigma-delta Modulation --- p.29Chapter 2.4. --- Continuous-time Sigma-delta Modulation --- p.29Chapter 2.5. --- IF-input Complex Analog to Digital Converter --- p.31Chapter 2.6. --- Image Rejection --- p.32Chapter 2.7. --- Integrated Mixer --- p.36Chapter Chapter 3 --- High Level Modeling and Simulation --- p.39Chapter 3.1. --- Introduction --- p.39Chapter 3.2. --- System Level Sigma-delta Modulator Design --- p.40Chapter 3.3. --- Continuous-time NTF Generation --- p.46Chapter 3.4. --- Discrete-time Sigma-delta Modulator Modeling --- p.50Chapter 3.5. --- Continuous-time Sigma-delta Modulator Modeling --- p.52Chapter 3.6. --- Modeling of Nonidealities --- p.53Chapter 3.7. --- High Level Simulation Results --- p.58Chapter Chapter 4 --- Transistor Level Implementation of the Complex Modulator and Layout --- p.65Chapter 4.1. --- Introduction --- p.65Chapter 4.2. --- IF Input Complex Modulator --- p.65Chapter 4.3. --- High IR IF Input Complex Modulator Design --- p.67Chapter 4.4. --- System Design --- p.73Chapter 4.5. --- Building Blocks Design --- p.77Chapter 4.5.1. --- Transconductor Design --- p.77Chapter 4.5.2. --- RC Integrator Design --- p.87Chapter 4.5.3. --- Gm-C Integrator Design --- p.90Chapter 4.5.4. --- Voltage to Current Converter --- p.95Chapter 4.5.5. --- Current Comparator Design --- p.96Chapter 4.5.6. --- Dynamic Element Matching Design --- p.98Chapter 4.5.7. --- Mixer Design --- p.100Chapter 4.5.8. --- Clock Generator --- p.103Chapter 4.6. --- Transistor Level Simulation of the Design --- p.106Chapter 4.7. --- Layout of the Mixed Signal Design --- p.109Chapter 4.7.1. --- Layout Overview --- p.109Chapter 4.7.2. --- Capacitor layout --- p.110Chapter 4.7.3. --- Resistor Layout --- p.113Chapter 4.7.4. --- Power and Ground Routing --- p.114Chapter 4.7.5. --- OTA Layout --- p.115Chapter 4.7.6. --- Chip Layout --- p.117Chapter 4.8. --- PostLayout Simulation --- p.120Chapter 5. --- Chapter 5 Measurement Results and Improvement --- p.122Chapter 5.1. --- Introduction --- p.122Chapter 5.2. --- PCB Design --- p.123Chapter 5.3. --- Test Setup --- p.125Chapter 5.4. --- Measurement of SNR and IRR --- p.128Chapter 5.5. --- Discussion of the Chip Performance --- p.131Chapter 5.6. --- Design of Robust Sigma Delta Modulator --- p.139Chapter Chapter 6 --- Conclusion --- p.148Chapter 6.1. --- Conclusion --- p.148Chapter 6.2. --- Future Work --- p.150Bibliography --- p.151Appendix A Schematics of Building Blocks --- p.155Author's Publications --- p.15
Recommended from our members
Improved design techniques for low-voltage low-power switched-capacitor delta-sigma modulators
This dissertation investigates the constraints which arise when switched-capacitor
(SC) delta-sigma modulators are designed for low-voltage operation, targeting also low
power dissipation, and proposes methods of improving the performance and optimizing
for low power dissipation. This is accomplished by identifying critical elements whose
performance can lead to increased power dissipation, as well as the fundamental
limitations of available analog circuit techniques. A prototype was designed and
fabricated, which reflected these findings, and therefore exhibited good performance and
nearly optimum power dissipation.
One of the key performance parameters is the dc gain of the amplifier in the first
stage; it should be high. This is necessary for high linearity and low quantization noise
leakage. In low-voltage operation, it may become impractical to use conventional
topologies employing cascoding techniques (e.g., folded-cascode) which provide high
gain in one single stage. Rather, cascaded structures have to be used. The disadvantage of
the latter is the necessity for frequency compensation which results in increased power
dissipation. Hence, another objective of this work is to exploit techniques which
compensate for the open-loop gain characteristic of the amplifier (dc gain and
nonlinearity), thus permitting the utilization of single-stage low-gain topologies.
Predictive correlated double sampling is one of such techniques and is analyzed in detail
Low power low voltage quadrature RC oscillators for modern RF receivers
Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThis thesis proposes a study of three different RC oscillators, two relaxation and a ring oscillator. All the circuits are implemented using UMC 130 nm CMOS technology with a supply voltage of 1.2 V.
We present a wideband MOS current/voltage controlled quadrature oscillator constituted
by two multivibrators. Two different forms of coupling named, soft (traditional)and hard (proposed) are differentiated and investigated. It is found that hard coupling
reduces the quadrature error and results in a low phase-noise (about 2 dB improvement)
with respect to soft coupling. The behaviour of the singular and coupled multivibrators
is investigated, when an external synchronizing harmonic is applied.
We introduce a new RC relaxation oscillator with pulse self biasing, to reduce power
consumption, and with harmonic ltering and resistor feedback, to reduce phase-noise.
The designed circuit has a very low phase-noise, -132.6 dBc/Hz @ 10 MHz offset, and
the power consumption is only 1 mW, which leads to a gure of merit (FOM) of -159.1
dBc/Hz.
The nal circuit is a two integrator fully implemented in CMOS technology, with low
power consumption. The respective layout is made and occupies a total area of5.856x10-3
mm2, post-layout simulation is also done
Analysis and design of low-power data converters
In a large number of applications the signal processing is done exploiting both
analog and digital signal processing techniques. In the past digital and analog
circuits were made on separate chip in order to limit the interference and other
side effects, but the actual trend is to realize the whole elaboration chain on a
single System on Chip (SoC). This choice is driven by different reasons such as the
reduction of power consumption, less silicon area occupation on the chip and also
reliability and repeatability. Commonly a large area in a SoC is occupied by digital
circuits, then, usually a CMOS short-channel technological processes optimized to
realize digital circuits is chosen to maximize the performance of the Digital Signal
Proccessor (DSP). Opposite, the short-channel technology nodes do not represent
the best choice for analog circuits. But in a large number of applications, the signals
which are treated have analog nature (microphone, speaker, antenna, accelerometers,
biopotential, etc.), then the input and output interfaces of the processing chip are
analog/mixed-signal conversion circuits. Therefore in a single integrated circuit (IC)
both digital and analog circuits can be found. This gives advantages in term of total
size, cost and power consumption of the SoC. The specific characteristics of CMOS
short-channel processes such as:
• Low breakdown voltage (BV) gives a power supply limit (about 1.2 V).
• High threshold voltage VTH (compared with the available voltage supply) fixed
in order to limit the leakage power consumption in digital applications (of the
order of 0.35 / 0.4V), puts a limit on the voltage dynamic, and creates many
problems with the stacked topologies.
• Threshold voltage dependent on the channel length VTH = f(L) (short channel
effects).
• Low value of the output resistance of the MOS (r0) and gm limited by speed
saturation, both causes contribute to achieving a low intrinsic gain gmr0 = 20
to 26dB.
• Mismatch which brings offset effects on analog circuits.
make the design of high performance analog circuits very difficult. Realizing lowpower
circuits is fundamental in different contexts, and for different reasons: lowering
the power dissipation gives the capability to reduce the batteries size in mobile
devices (laptops, smartphones, cameras, measuring instruments, etc.), increase the
life of remote sensing devices, satellites, space probes, also allows the reduction of
the size and weight of the heat sink. The reduction of power dissipation allows the
realization of implantable biomedical devices that do not damage biological tissue.
For this reason, the analysis and design of low power and high precision analog
circuits is important in order to obtain high performance in technological processes
that are not optimized for such applications. Different ways can be taken to reduce
the effect of the problems related to the technology:
• Circuital level: a circuit-level intervention is possible to solve a specific problem
of the circuit (i.e. Techniques for bandwidth expansion, increase the gain,
power reduction, etc.).
• Digital calibration: it is the highest level to intervene, and generally going to
correct the non-ideal structure through a digital processing, these aims are
based on models of specific errors of the structure.
• Definition of new paradigms.
This work has focused the attention on a very useful mixed-signal circuit: the
pipeline ADC. The pipeline ADCs are widely used for their energy efficiency in
high-precision applications where a resolution of about 10-16 bits and sampling
rates above hundreds of Mega-samples per second (telecommunication, radar, etc.)
are needed. An introduction on the theory of pipeline ADC, its state of the art
and the principal non-idealities that affect the energy efficiency and the accuracy
of this kind of data converters are reported in Chapter 1. Special consideration is
put on low-voltage low-power ADCs. In particular, for ADCs implemented in deep
submicron technology nodes side effects called short channel effects exist opposed to
older technology nodes where undesired effects are not present. An overview of the
short channel effects and their consequences on design, and also power consuption
reduction techniques, with particular emphasis on the specific techniques adopted
in pipelined ADC are reported in Chapter 2. Moreover, another way may be
undertaken to increase the accuracy and the efficiency of an ADC, this way is the
digital calibration. In Chapter 3 an overview on digital calibration techniques, and
furthermore a new calibration technique based on Volterra kernels are reported. In
some specific applications, such as software defined radios or micropower sensor,
some circuits should be reconfigurable to be suitable for different radio standard
or process signals with different charateristics. One of this building blocks is the
ADC that should be able to reconfigure the resolution and conversion frequency. A
reconfigurable voltage-scalable ADC pipeline capable to adapt its voltage supply
starting from the required conversion frequency was developed, and the results are
reported in Chapter 4. In Chapter 5, a pipeline ADC based on a novel paradigm for
the feedback loop and its theory is described
Cutting Edge Nanotechnology
The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters
34th Midwest Symposium on Circuits and Systems-Final Program
Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society.
Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi