63 research outputs found
A very high speed bandpass continous time sigma delta modulator for RF receiver front end A/D conversion
Master'sMASTER OF ENGINEERIN
Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR
This paper presents the design and implementation
of a fourth-order band-pass continuous-time modulator intended
for the digitization of radio-frequency signals in softwaredefined-
radio applications. The modulator architecture consists
of two Gm-LC resonators with a tunable notch frequency and
a 4-bit flash analog-to-digital converter in the forward path and
a non-return-to-zero digital-to-analog converter with a finiteimpulse-
response filter in the feedback path. Both system-level
and circuit-level reconfiguration techniques are included in order
to allow the modulator to digitize signals placed at different
carrier frequencies, from 450MHz to 950MHz. A proper synthesis
methodology of the loop-filter coefficients at system level and
the use of inverter-based switchable transconductors allow to
optimize the performance in terms of robustness to circuit errors,
stability and power consumption. The circuit, implemented in 65-
nm CMOS, can digitise signals with up to 57-dB SNDR within a
40-MHz bandwidth, with an adaptive power dissipation of 16.7-
to-22.8 mW and a programmable 1.2/2GHz clock rate1
A 2 GHz Bandpass Analog to Digital Delta-sigma Modulator for CDMA Receivers with 79 DB Dynamic Range in 1.23 MHz Bandwidth
This paper presents the design of a second-order single-bit analog-to-digital continuous-time delta-sigma modulator that can be used in wireless CDMA receivers. The continuous-time delta-sigma modulator samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79-dB signal-to-noise ratio (SNR) over a 1.23-MHz bandwidth. The continuous-time delta-sigma modulator was fabricated in a 0.18- m 1-poly 6-metal, CMOS technology and has an active area of approximately 0.892 mm2 . The delta-sigma modulator\u27s critical performance speciïŹcations are derived from the CDMA receiver speciïŹcations
High Performance Integrated Circuit Blocks for High-IF Wideband Receivers
Due to the demand for highâperformance radio frequency (RF) integrated circuit
design in the past years, a systemâonâchip (SoC) that enables integration of analog and
digital parts on the same die has become the trend of the microelectronics industry. As
a result, a major requirement of the next generation of wireless devices is to support
multiple standards in the same chipâset. This would enable a single device to support
multiple peripheral applications and services.
Based on the aforementioned, the traditional superheterodyne frontâend
architecture is not suitable for such applications as it would require a complete receiver
for each standard to be supported. A more attractive alternative is the highintermediate
frequency (IF) radio architecture. In this case the signal is digitalized at an
intermediate frequency such as 200MHz. As a consequence, the baseband operations,
such as downâconversion and channel filtering, become more power and area efficient
in the digital domain. Such architecture releases the specifications for most of the frontâend building blocks, but the linearity and dynamic range of the ADC become the
bottlenecks in this system. The requirements of large bandwidth, high frequency and
enough resolution make such ADC very difficult to realize. Many ADC architectures
were analyzed and ContinuousâTime Bandpass SigmaâDelta (CTâBPâÎŁÎ) architecture was
found to be the most suitable solution in the highâIF receiver architecture since they
combine oversampling and noise shaping to get fairly high resolution in a limited
bandwidth.
A major issue in continuousâtime networks is the lack of accuracy due to powervoltageâ
temperature (PVT) tolerances that lead to over 20% pole variations compared
to their discreteâtime counterparts. An optimally tuned BP ÎŁÎ ADC requires correcting
for center frequency deviations, excess loop delay, and DAC coefficients. Due to these
undesirable effects, a calibration algorithm is necessary to compensate for these
variations in order to achieve high SNR requirements as technology shrinks.
In this work, a novel linearization technique for a Wideband LowâNoise
Amplifier (LNA) targeted for a frequency range of 3â7GHz is presented. Postâlayout
simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm,
respectively. The power consumption of the LNA is 5.8mA from 2V.
Secondly, the design of a CMOS 6th order CT BPâÎŁÎ modulator running at 800
MHz for HighâIF conversion of 10MHz bandwidth signals at 200 MHz is presented. A
novel transconductance amplifier has been developed to achieve high linearity and high
dynamic range at high frequencies. A 2âbit quantizer with offset cancellation is alsopresented. The sixthâorder modulator is implemented using 0.18 um TSMC standard
analog CMOS technology. Postâlayout simulations in cadence demonstrate that the
modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth.
The modulatorâs static power consumption is 107mW from a supply power of ± 0.9V.
Finally, a calibration technique for the optimization of the Noise Transfer
Function CT BP ÎŁÎ modulators is presented. The proposed technique employs two test
tones applied at the input of the quantizer to evaluate the noise transfer function of
the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually
available in mixedâmode systems. Once the ADC output bit stream is captured,
necessary information to generate the control signals to tune the ADC parameters for
best SignalâtoâQuantization Noise Ratio (SQNR) performance is extracted via Leastâ
Mean Squared (LMS) softwareâbased algorithm. Since the two tones are located
outside the band of interest, the proposed global calibration approach can be used
online with no significant effect on the inâband content
A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ÎŁÎ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver
This document is the Accepted Manuscript version of the following article: Junfeng Zhang, Yang Xu, Zehong Zhang, Yichuang Sun, Zhihua Wang, and Baoyong Chi, âA 10-b Fourth-Order Quadrature Bandpass Continuous-Time ÎŁÎ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiverâ, IEEE Transactions on Microwave Theory and Practice, Vol. 65 (4): 1303-1314, first published online 16 February 2017. The version of record is available online at DOI: 10.1109/TMTT.2017.266237, Published by IEEE. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A fourth-order quadrature bandpass continuous-time sigma-delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital-analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.Peer reviewe
Low Power Continuous-time Bandpass Delta-Sigma Modulators.
Low power techniques for continuous-time bandpass delta-sigma modulators (CTBPDSMs) are introduced. First, a 800MS/s low power 4th-order CTBPDSM with 24MHz bandwidth at 200MHz IF is presented. A novel power-efficient resonator with a single amplifier is used in the loopfilter. A single op-amp resonator makes use of positive feedback to increase the quality factor. Also, a new 4th-order architecture is introduced for system simplicity and low power. Low power consumption and a simple modulator structure are achieved by reducing the number of feedback DACs. This modulator achieves 58dB SNDR, and the total power consumption is 12mW.
Second, a 6th-order CTBPDSM with duty cycle controlled DACs is presented. This prototype introduces new architecture for low power consumption and other important features. Duty cycle control enables the use of a single DAC per resonator without degrading the signal transfer function (STF), and helps to lower power consumption, low area, and thermal noise. This ADC provides input signal filtering, and increases the dynamic range by reducing the peaking in the STF. Furthermore, the center frequency is tunable so that the CTBPDSM is more useful in the receiver. The prototype second modulator achieves 69dB SNDR, and consumes 35mW, demonstrating the best FoM of 320fJ/conv.-step for CTBPDSMs using active resonators.
The techniques introduced in this research help CTBPDSMs have good power efficiency compared with the other kinds of ADCs, and make the implement of a software-defined radio architecture easier which is appropriate for the future multiple standard radio receivers without a power penalty.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98001/1/hichae_1.pd
Micromechanical resonator based bandpass sigma-delta modulator
Master'sMASTER OF ENGINEERIN
The design of a 250MHz CMOS bandpass sigma-delta A/D modulator with continuous-time circuitry
Master'sMASTER OF ENGINEERIN
Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements
The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver
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