Recent Advances in Ambipolar Transistors for Functional Applications

Ambipolar transistors represent a class of transistors where positive (holes) and negative (electrons) charge carriers both can transport concurrently within the semiconducting channel. The basic switching states of ambipolar transistors are comprised of common offâ state and separated onâ state mainly impelled by holes or electrons. During the past years, diverse materials are synthesized and utilized for implementing ambipolar charge transport and their further emerging applications comprising ambipolar memory, synaptic, logic, and lightâ emitting transistors on account of their special bidirectional carrierâ transporting characteristic. Within this review, recent developments of ambipolar transistor field involving fundamental principles, interface modifications, selected semiconducting material systems, device structures, ambipolar characteristics, and promising applications are highlighted. The existed challenges and prospective for researching ambipolar transistors in electronics and optoelectronics are also discussed. It is expected that the review and outlook are well timed and instrumental for the rapid progress of academic sector of ambipolar transistors in lighting, display, memory, as well as neuromorphic computing for artificial intelligence.Ambipolar transistors represent transistors that allow synchronous transport of electrons and holes and their accumulation within semiconductors. This review provides a comprehensive summary of recent advances in various semiconducting materials realized in ambipolar transistors and their functional memory, synapse, logic, as well as lightâ emitting applications.Peer Reviewedhttps://deepblue.lib.umich.edu/bitstream/2027.42/151885/1/adfm201902105_am.pdfhttps://deepblue.lib.umich.edu/bitstream/2027.42/151885/2/adfm201902105.pd

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Nanoscale electronic devices based on the hybrid stacks of two-dimensional materials and ferroelectric metal oxides

Further scaling of complementary metal-oxide-semiconductor (CMOS) dimensions will soon lead to a tremendous rise in power consumption while limited gain in the performance of integrated circuits. “Beyond-CMOS” devices, based on two-dimensional (2D) materials, can potentially overcome these limitations and further improve the performance, reduce energy consumption, and add novel functionalities to the CMOS platform. In this Ph.D. dissertation, we investigated energy efficient electronic devices based on a new hybrid material platform consisting of two-dimensional materials and ferroelectric metal oxides. The ferroelectric metal oxides provide programmable and non-volatile doping in the 2D materials, while the atomically thin body in 2D materials enables strong electrostatic control over the channel by the polarized ferroelectric metal oxides. We design and demonstrate a new type of classifier using ferroelectric graphene transistors, which can perform the “comparison” function in the analog domain instead of the traditional digital domain. This new type of classifier utilizes the ambipolar transport and zero bandgap of the graphene to perform the absolute difference function, |A-B|, directly. Unlike the image classifier based on silicon CMOS, the classifier based on ferroelectric graphene transistors only needs ONE transistor per pixel, which will significantly reduce chip area and energy consumption. More importantly, the embedded ferroelectric layer in the graphene transistor enables the non-volatile storage of the target image inside the analog device. Therefore, a single graphene transistor can perform both image storage and comparison functions concurrently. This in-memory computing will eliminate the need for frequent image loading/unloading, which will further reduce the power consumption related to the data transfer. We also explored non-volatile reconfigurable devices based on the hybrid stacks of ferroelectric materials and 2D materials. In traditional silicon CMOS, once the device is fabricated, its function is fixed as either an n-type or a p-type transistor. In this work, we show that functionality of this new type of device can be dynamically reconfigured during operation and the reconfiguration is non-volatile and reprogrammable. We have successfully demonstrated the electrostatic controlled reconfigurable devices based on black phosphorus and non-volatile reconfigurable devices based on molybdenum telluride and ferroelectric hafnium zirconium oxides. These reconfigurable devices will enable the logic circuits to evolve their functions on-demand. The 3D monolithic integration of these reconfigurable devices/circuits and memory blocks will enable in-memory computing and reduce the energy consumption and latency related to the transportation of “Big Data”. This work will open a new path toward the design of novel nano-function circuits based on unique material properties that are absent in traditional circuits based on CMOS logic transistors and Von Neumann architectures. These new devices will also enable a new computing paradigm, where the process latency and energy consumption will no longer be limited by the memory bottleneck

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Direct Photolithography on Molecular Crystals for High Performance Organic Optoelectronic Devices

Organic crystals are generated via the bottom-up self-assembly of molecular building blocks which are held together through weak noncovalent interactions. Although they revealed extraordinary charge transport characteristics, their labile nature represents a major drawback toward their integration in optoelectronic devices when the use of sophisticated patterning techniques is required. Here we have devised a radically new method to enable the use of photolithography directly on molecular crystals, with a spatial resolution below 300 nm, thereby allowing the precise wiring up of multiple crystals on demand. Two archetypal organic crystals, i.e., p-type 2,7-diphenyl[1]benzothieno[3,2-b][1]benzothiophene (Dph-BTBT) nanoflakes and n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8) nanowires, have been exploited as active materials to realize high-performance top-contact organic field-effect transistors (OFETs), inverter and p–n heterojunction photovoltaic devices supported on plastic substrate. The compatibility of our direct photolithography technique with organic molecular crystals is key for exploiting the full potential of organic electronics for sophisticated large-area devices and logic circuitries, thus paving the way toward novel applications in plastic (opto)electronics

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. With all these innovations and efforts, the transistor size is approaching the natural limitations of materials in the near future. The circuits are expected to compute in a more efficient way. From this perspective, new device concepts are desirable to exploit additional functionality. On the other hand, with the continuously increased device density on the chips, reducing the power consumption has become a key concern in IC design. To overcome the limitations of Complementary Metal-Oxide-Semiconductor (CMOS) technology in computing efficiency and power reduction, this thesis introduces the multiple- independent-gate Field-Effect Transistors (FETs) with silicon nanowires and FinFET structures. The device not only has the capability of polarity control, but also provides dual-threshold- voltage and steep-subthreshold-slope operations for power reduction in circuit design. By independently modulating the Schottky junctions between metallic source/drain and semiconductor channel, the dual-threshold-voltage characteristics with controllable polarity are achieved in a single device. This property is demonstrated in both experiments and simulations. Thanks to the compact implementation of logic functions, circuit-level benchmarking shows promising performance with a configurable dual-threshold-voltage physical design, which is suitable for low-power applications. This thesis also experimentally demonstrates the steep-subthreshold-slope operation in the multiple-independent-gate FETs. Based on a positive feedback induced by weak impact ionization, the measured characteristics of the device achieve a steep subthreshold slope of 6 mV/dec over 5 decades of current. High Ion/Ioff ratio and low leakage current are also simultaneously obtained with a good reliability. Based on a physical analysis of the device operation, feasible improvements are suggested to further enhance the performance. A physics-based surface potential and drain current model is also derived for the polarity-controllable Silicon Nanowire FETs (SiNWFETs). By solving the carrier transport at Schottky junctions and in the channel, the core model captures the operation with independent gate control. It can serve as the core framework for developing a complete compact model by integrating advanced physical effects. To summarize, multiple-independent-gate SiNWFETs and FinFETs are extensively studied in terms of fabrication, modeling, and simulation. The proposed device concept expands the family of polarity-controllable FETs. In addition to the enhanced logic functionality, the polarity-controllable SiNWFETs and FinFETs with the dual-threshold-voltage and steep-subthreshold-slope operation can be promising candidates for future IC design towards low-power applications

Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before