Improved offline calibration for DAC mismatch in low OSR Sigma Delta ADCs with distributed feedback

We present an offline calibration method to correct the non-linearity due to DAC element mismatch in distributed feedback SigmaDelta-modulation A/D-converters. The improvement over previous methods is that not only the first feedback DAC is calibrated, but also the DACs that are coupled to later stages can be calibrated as well. This is needed in the case of Sigma Delta modulators with a low OSR, where the contribution of the second feedback DAC should not be neglected. The technique is based on a calibration measurement with a two-tone input signal

Multibit delta sigma modulator with noise shaping dynamic element matching

Ph.DDOCTOR OF PHILOSOPH

High efficiency delta-sigma modulation data converters

Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common everyday life. Wide signal bandwidth, high linearity and dynamic range, and low power dissipation are required of embedded data converters that are the performance-limiting key building blocks of those systems. Thus, power-efficient and highly-linear data conversion over wide range of signal bands is essential to get the full benefits from device scaling. This continued trend keeps innovation in the design of data converter continuing. Traditionally, delta-sigma modulation data converters proved to be very effective in applications where high resolution was necessary in a relatively narrow signal band. There have been active research efforts across academia and industry on the extension of achievable signal bandwidth without compromising the performance of these data converters. In this dissertation, architectural innovations, combined with effective design techniques for delta-sigma modulation data converters, are presented to overcome the associated limitations. The effectiveness of the proposed approaches is demonstrated by test results for the following state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma modulation D/A converter with headphone driver; (2) an 88 dB ring-coupled delta-sigma ADC with 1.9 MHz bandwidth and -102.4 dB THD; (3) a multi-cell noise-coupled delta-sigma ADC with 1.9 MHz bandwidth, 88 dB DR, and -98 dB THD; (4) an 8.1 mW, 82 dB self-coupled delta-sigma ADC with 1.9 MHz bandwidth and -97 dB THD; (5) a noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR; (6) a noise-coupled time-interleaved delta-sigma ADC with 2.5 MHz bandwidth, -104 dB THD, and 81 dB SNDR. As an extension of this research, two novel architectures for efficient double-sampling delta-sigma ADCs and improved low-distortion delta-sigma ADC are proposed, and validated by extensive simulations.Keywords: improved low-distortion modulator, time interleaving, data converter, multi-cell ADC, efficient double sampling, noise coupling, delta-sigma modulatio

Low-power double-sampled delta-sigma modulator for broadband applications

High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (ΔΣ) ADCs are able to achieve wide-band operation and high accuracy simultaneously. At first in this thesis, two novel techniques which can be applied to high performance ΔΣ ADC design are proposed. The first one is a modulator architectural innovation that is able to effectively solve the feedback timing constraints in a double-sampled ΔΣ modulator. The second one is a transistor level improvement to reduce the hardware consumption in a standard Date Weighted Averaging (DWA) realization. Next, charge-pump (CP) based switched-capacitor (SC) integrator is discussed. A cross-coupling technique is proposed to eliminate parasitic capacitor effect in a CP based SC integrator. Also design methodologies are introduced to incorporate a modified CP based SC integrator into a low-distortion ΔΣ modulator. A second-order ΔΣ modulator was designed and simulated to verify the proposed modulator topology. Finally, design of a double-sampled broadband 12-bit ΔΣ modulator is presented. To achieve very low power consumption, this modulator utilizes the following two key design techniques: 1. Double sampled integrator to increase the effective over-sampling ratio. 2. Capacitor reset technique allows the use of only one feedback DAC at the front end of the modulator to completely eliminate the quantization noise folding back. A 2+2 cascaded topology with 3-bit internal quantizer is used in this ΔΣ modulator to adequately suppress the quantization noise while guarantee the loop stability. This ΔΣ modulator was fabricated in a 90nm digital CMOS process and achieves an SNDR of 70dB within a 5MHz signal bandwidth. The modulator occupies a silicon area of 0.5mm² and consumes 10mW with a supply voltage of 1.2V

Design of a Time Based Analog to Digital Converter

Analog to digital converter (ADC) plays a very important role in any mixed analog/digital system. Because digital CMOS technology can take advantage of technology scaling, system designers try to increase the percentage of the digital part of the system. This means moving the ADC more and more towards the input of the system which results in making the role of the ADC more and more critical. With technology scaling, the switching characteristics of MOS transistors offer superb timing accuracy at high frequencies. This makes the time based analog to digital converter (TADC) a good alternative to the conventional ADCs in sub-micron region. In this thesis, an all digital TADC structure is proposed. This TADC is based on an analog to time converter (ATC), followed by a time to digital converter (TDC). The TDC is based on sigma-delta modulation. A non-linear multi-bit internal quantizer in sigma-delta modulator is used to counteract the nonlinearity introduced when the VCO is used as the ATC. The novel TADC also uses an implicit sample and hold (S/H) circuit to reduce area. Dynamic element matching (DEM) is used to improve the robustness of the system against random mismatch in the multi-bit quantizer. Both first and second order sigma-delta modulator TADC are proposed. Simulations and measurements on the proposed TADC are provided. Measurements, from a prototype chip fabricated using 0.13um CMOS technology, show that the first order TADC has achieved a dynamic range of 11 bits for a bandwidth of 2MHz. While simulation results show a dynamic range of 12 bit. Simulations show that the second order TADC has achieved a dynamic range of 12bit for a bandwidth of 20MHz