High efficiency wideband low-power delta-sigma modulators

Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling in CMOS technology and architectural and circuit level design innovations, they have even become popular for wideband, high dynamic range applications such as wired and wireless communication systems. Therefore, power efficient wideband low power delta-sigma data converters that bridges analog and digital have become mandatory for popular mobile applications today. In this dissertation, two architectural innovations and a development and realization of a state-of-the-art delta-sigma analog to digital converter with effective design techniques in both architectural and circuit levels are presented. The first one is timing-relaxed double noise coupling which effectively provides 2nd order noise shaping in the noise transfer function and overcomes stringent timing requirement for quantization and DEM. The second one presented is a noise shaping SAR quantizer, which provides one order of noise shaping in the noise transfer function. It uses a charge redistribution SAR quantizer and is applied to a timing-relaxed lowdistortion delta-sigma modulator which is suitable for adopting SAR quantizer. Finally a cascade switched capacitor delta-sigma analog-to-digital converter suitable for WLAN applications is presented. It uses a noise folding free double sampling technique and an improved low-distortion architecture with an embedded-adder integrator. The prototype chip is fabricated with a double poly, 4 metal, 0.18μm CMOS process. The measurement result achieves 73.8 dB SNDR over 10 MHz bandwidth. The figure of merit defined by FoM = P/(2 x BW x 2[superscript ENOB]) is 0.27 pJ/conv-step. The measurement results indicate that the proposed design ideas are effective and useful for wideband, low power delta-sigma analog-to-digital converters with low oversampling ratio

Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ

Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters

There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages of the delta-sigma ADC including relaxed anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and most importantly, reduced sensitivity to analog imperfections. In this thesis, several structures and design techniques are developed for the implementation of continuoustime (CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total power consumption, reduce the design complexity, and decrease the chip die area of delta-sigma modulators. First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad (SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of an Nth-order CT delta-sigma modulator, it requires only half the number of active amplifiers and feed-forward branches used in the conventional modulator architecture, thus decreasing the power consumption and area by reducing the number of amplifiers. The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder due to the reduced number of feedforward branches to its summing block. As a sequence, it consumes less power compared to a conventional CT adder. With a 130-nm CMOS technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz signal bandwidth and analog power dissipation lower than 12 mW. Presented as the second scheme to save power consumption and chip die area in ΔΣ modulators is a new stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique shares all the active blocks of the modulator second stage with its first stage during the two non-overlapping clock phases. Measurement results show that the modulator designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz conversion bandwidth dissipating less than 9 mW analog power

Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays

Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop delays (SLD) technique can relax the speed requirements of the quantizer and the dynamic element matching (DEM) block, and eliminate the active adder. An implemented 0.18 um CMOS prototype with the proposed architecture provided 81.6 dB SNDR, 81.8 dB dynamic range, and -95.6 dB THD in a signal bandwidth of 4 MHz. It dissipates 19.2 mW with a 1.6 V power supply. The conventional low-distortion ADC was also implemented on the same chip for comparison. The new circuit has superior performance, and dissipates 25% less power (19.2 mW vs. 24.9 mW) than the conventional one. The figure-of-merit for the ADC with SLD is among the best reported for wideband discrete-time ADCs, and is almost 40% better than that of the conventional ADC. The second project describes two techniques to enhance the noise shaping function in the proposed low-distortion ΔΣ modulator with shifted loop delays. One is self-noise coupling based on low-distortion ΔΣ structure; the other is noise-coupled time-interleaved ΔΣ modulator. Both architectures use shifted loop delays to relax the critical timing constraints in the modulator feedback path, then to save power consumption of each block in the modulators. Two ΔΣ ADCs were analyzed and simulated in a 0.18um CMOS technology. The simulation results highly verify the effectiveness of the proposed structure. The third system describes the design technique for double-sampled wideband ΔΣ ADCs with shifted loop delays (SLD). The added loop delay in the feedback branch relaxes the critical timing for DEM logic. Delay shifting can be combined with such useful techniques as low-distortion circuitry and noise coupling for wideband ΔΣ modulators. The presented techniques relax the timing for inherent quantization delay, reduce the speed requirements for the critical circuit blocks, and achieve power efficiency by replacing the power-hungry blocks normally used in the modulators. Analysis of all architectures allows the choice of the most power-efficient topology for a wideband ΔΣ modulator. The proposed second-order and third-order ΔΣ modulators were designed and simulated to verify the effectiveness of the shifted loop delays techniques.Keywords: Noise-shaping, Shifted Loop Delays, Delta-Sigma Modulator, Low-distortion, AD

Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected

Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems

For today’s ubiquitous portable devices, innovative integrated circuits with high performance yet very low power are necessary. As these devices are used to communicate and sense real world signals in the environment, analog-to-digital converters (ADC) and systems are the key interface circuits needed to digitize the sensed information and they represent one of the most challenging aspects in the overall design. Fundamentally, this is due to the inherent imperfections in integrated circuit process technology because they cause degradations in the ADC performance. In this thesis, noise-shaping techniques are used to mitigate analog inaccuracies such as non-linearity and mismatch. These approaches are applied to ΔΣ analog-to-digital based systems. Two systems are presented in this work. The first is an architectural technique to highlight the benefits of low power, highly digital VCO-based analog-to-digital converters. It overcomes the limited SFDR due to VCO non-linearity. In this approach, a multi-loop delta-sigma (ΔΣ) ADC architecture is introduced that has a multi-rated VCO-based ADC in its second stage. A custom IC prototype of this architecture fabricated in a 130nm 1P8M CMOS process achieves 77.3dB signal-to-noise-ratio (SNR) over a 4MHz signal bandwidth with a power consumption of 13.8mW. The second system includes a new dynamic element matching (DEM) algorithm in the reference generating circuit of a ΔΣ modulator. The most basic DEM algorithm known as data weighted averaging (DWA) increases in-band noise due to intermodulation between the DEM tone and quantization error. In the proposed technique, by completing an integer multiple of the DEM cycles within one ΣΔ cycle, the DEM tone is moved to an integer multiple of the ΣΔ sample rate. As a result, with no additional circuitry or power consumption, the new DEM technique prevents any increase in the in-band noise. To prove its effectiveness, the DEM algorithm is embedded in a temperature-to-digital Converter (TDC) which requires a high precision reference. This TDC consists of a BJT-based temperature sensor followed by a 2nd-order feed-forward ΔΣ ADC as a readout circuit. It is fabricated in an 180nm 1P5M CMOS process consuming 5µA current from 1.4V supply voltage achieving resolution of 25mK/Conversion

High efficiency delta-sigma modulation data converters

Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common everyday life. Wide signal bandwidth, high linearity and dynamic range, and low power dissipation are required of embedded data converters that are the performance-limiting key building blocks of those systems. Thus, power-efficient and highly-linear data conversion over wide range of signal bands is essential to get the full benefits from device scaling. This continued trend keeps innovation in the design of data converter continuing. Traditionally, delta-sigma modulation data converters proved to be very effective in applications where high resolution was necessary in a relatively narrow signal band. There have been active research efforts across academia and industry on the extension of achievable signal bandwidth without compromising the performance of these data converters. In this dissertation, architectural innovations, combined with effective design techniques for delta-sigma modulation data converters, are presented to overcome the associated limitations. The effectiveness of the proposed approaches is demonstrated by test results for the following state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma modulation D/A converter with headphone driver; (2) an 88 dB ring-coupled delta-sigma ADC with 1.9 MHz bandwidth and -102.4 dB THD; (3) a multi-cell noise-coupled delta-sigma ADC with 1.9 MHz bandwidth, 88 dB DR, and -98 dB THD; (4) an 8.1 mW, 82 dB self-coupled delta-sigma ADC with 1.9 MHz bandwidth and -97 dB THD; (5) a noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR; (6) a noise-coupled time-interleaved delta-sigma ADC with 2.5 MHz bandwidth, -104 dB THD, and 81 dB SNDR. As an extension of this research, two novel architectures for efficient double-sampling delta-sigma ADCs and improved low-distortion delta-sigma ADC are proposed, and validated by extensive simulations.Keywords: improved low-distortion modulator, time interleaving, data converter, multi-cell ADC, efficient double sampling, noise coupling, delta-sigma modulatio

Analysis of Current Conveyor based Switched Capacitor Circuits for Application in ∆Σ Modulators

The reduction in supply voltage, loss of dynamic range and increased noise prevent the analog circuits from taking advantage of advanced technologies. Therefore the trend is to move all signal processing tasks to digital domain where advantages of technology scaling can be used. Due to this, there exists a need for data converters with large signal bandwidths, higher speeds and greater dynamic range to act as an interface between real world analog and digital signals. The Delta Sigma (∆Σ) modulator is a data converter that makes use of large sampling rates and noise shaping techniques to achieve high resolution in the band of interest. The modulator consists of analog integrators and comparators which create a modulated digital bit stream whose average represents the input value. Due to their simplicity, they are popular in narrow band receivers, medical and sensor applications. However Operational Amplifiers (Op-Amps) or Operational Transconductance Amplifiers (OTAs), which are commonly used in data converters, present a bottleneck. Due to low supply voltages, designers rely on folded cascode, multistage cascade and bulk driven topologies for their designs. Although the two stage or multistage cascade topologies offer good gain and bandwidth, they suffer from stability problems due to multiple stages and feedback requiring large compensation capacitors. Therefore other low voltage Switched-Capacitor (SC) circuit techniques were developed to overcome these problems, based on inverters, comparators and unity gain buffers. In this thesis we present an alternative approach to design of ∆Σ modulators using Second Generation Current Conveyors (CCIIs). The important feature of these modulators is the replacement of the traditional Op-Amp based SC integrators with CCII based SC integrators. The main design issues such as the effect of the non-idealities in the CCIIs are considered in the operation of SC circuits and solutions are proposed to cancel them. Design tradeoffs and guidelines for various components of the circuit are presented through analysis of existing and the proposed SC circuits. A two step adaptive calibration technique is presented which uses few additional components to measure the integrator input output characteristic and linearize it for providing optimum performance over a wide range of sampling frequencies while maintaining low power and area. The presented CCII integrator and calibration circuit are used in the design of a 4th order (2-2 cascade) ∆Σ modulator which has been fabricated in UMC 90nm/1V technology through Europractice. Experimental values for Signal to Noise+Distortion Ratio (SNDR), Dynamic Range (DR) and Figure Of Merit (FOM) show that the modulator can compete with state of art reconfigurable Discrete-Time (DT) architectures while using lower gain stages and less design complexity

High-Speed Delta-Sigma Data Converters for Next-Generation Wireless Communication

In recent years, Continuous-time Delta-Sigma(CT-ΔΣ) analog-to-digital converters (ADCs) have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths greater than 15 MHz and higher resolution of 10 to 14 bits. This dissertation investigates the current state-of-the-art high-speed single-bit and multi-bit Continuous-time Delta-Sigma modulator (CT-ΔΣM) designs and their limitations due to circuit non-idealities in achieving the performance required for next-generation wireless standards. Also, we presented complete architectural and circuit details of a high-speed single-bit and multi-bit CT-ΔΣM operating at a sampling rate of 1.25 GSps and 640 MSps respectively (the highest reported sampling rate in a 0.13 μm CMOS technology node) with measurement results. Further, we propose novel hybrid ΔΣ architecture with two-step quantizer to alleviate the bandwidth and resolution bottlenecks associated with the contemporary CT-ΔΣM topologies. To facilitate the design with the proposed architecture, a robust systematic design method is introduced to determine the loop-filter coefficients by taking into account the non-ideal integrator response, such as the finite opamp gain and the presence of multiple parasitic poles and zeros. Further, comprehensive system-level simulation is presented to analyze the effect of two-step quantizer non-idealities such as the offset and gain error in the sub-ADCs, and the current mismatch between the MSB and LSB elements in the feedback DAC. The proposed novel architecture is demonstrated by designing a high-speed wideband 4th order CT-ΔΣ modulator prototype, employing a two-step quantizer with 5-bits resolution. The proposed modulator takes advantage of the combination of a high-resolution two-step quantization technique and an excess-loop delay (ELD) compensation of more than one clock cycle to achieve lower-power consumption (28 mW), higher dynamic range (\u3e69 dB) with a wide conversion bandwidth (20 MHz), even at a lower sampling rate of 400 MHz. The proposed modulator achieves a Figure of Merit (FoM) of 340 fJ/level