Discrete-Time Chaotic-Map Truly Random Number Generators: Design, Implementation, and Variability Analysis of the Zigzag Map

In this paper, we introduce a novel discrete chaotic map named zigzag map that demonstrates excellent chaotic behaviors and can be utilized in Truly Random Number Generators (TRNGs). We comprehensively investigate the map and explore its critical chaotic characteristics and parameters. We further present two circuit implementations for the zigzag map based on the switched current technique as well as the current-mode affine interpolation of the breakpoints. In practice, implementation variations can deteriorate the quality of the output sequence as a result of variation of the chaotic map parameters. In order to quantify the impact of variations on the map performance, we model the variations using a combination of theoretical analysis and Monte-Carlo simulations on the circuits. We demonstrate that even in the presence of the map variations, a TRNG based on the zigzag map passes all of the NIST 800-22 statistical randomness tests using simple post processing of the output data.Comment: To appear in Analog Integrated Circuits and Signal Processing (ALOG

Topics in chaotic secure communication

Results in nonlinear dynamics and chaos during this decade have been applied to problems in secure communications with limited success. Most of these applications have been based on the chaotic synchronization property discovered by Pecora and Carroll in 1989 [37]. Short [44, 45, 48] demonstrated the effectiveness of nonlinear dynamic (NLD) forecasting methods in breaking this class of communication schemes. In response, investigators have proposed enhancements to the basic synchronization technique in an attempt to improve the security properties. In this work two of these newer communication systems will be analyzed using NLD forecasting and other techniques to determine the level of security they provide. It will be shown that the transmitted waveform alone allows an eavesdropper to extract the message. During the course of this research, a new impulsively initialized, binary chaotic communication scheme has been developed, which eliminates the most significant weaknesses of its predecessors. This new approach is based on symbolic dynamics and chaotic control, and may be implemented using one-dimensional maps, which gives the designer more control over the statistics of the transmitted binary stream. Recent results in a certain class of one-dimensional chaotic maps will be discussed in this context. The potential for using NLD techniques in problems from standard digital communications will also be explored. The two problems which will be addressed are bit errors due to channel effects and co-channel interference. It will be shown that NLD reconstruction methods provide a way to exploit the short-term determinism that is present in these types of communication signals

Microcontroller-based random number generator implementation by using discrete chaotic maps

In recent decades, chaos theory has been used in different engineering applications of different disciplines. Discrete chaotic maps can be used in encryption applications for digital applications. In this study, firstly, Lozi, Tinkerbell and Barnsley Fern discrete chaotic maps are implemented based on microcontroller. Then, microcontroller based random number generator is implemented by using the three different two-dimensional discrete chaotic maps. The designed random number generator outputs are applied to NIST (National Institute of Standards and Technology) 800-22 and FIPS (Federal Information Processing Standard) tests for randomness validity. The random numbers are successful in all tests

New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation

This study aims to design a new architecture of the artificial neural networks (ANNs) using the Xilinx system generator (XSG) and its hardware co-simulation equivalent model using field programmable gate array (FPGA) to predict the behavior of Chua’s chaotic system and use it in hiding information. The work proposed consists of two main sections. In the first section, MATLAB R2016a was used to build a 3×4×3 feed forward neural network (FFNN). The training results demonstrate that FFNN training in the Bayesian regulation algorithm is sufficiently accurate to directly implement. The second section demonstrates the hardware implementation of the network with the XSG on the Xilinx artix7 xc7a100t-1csg324 chip. Finally, the message was first encrypted using a dynamic Chua system and then decrypted using ANN’s chaotic dynamics. ANN models were developed to implement hardware in the FPGA system using the IEEE 754 Single precision floating-point format. The ANN design method illustrated can be extended to other chaotic systems in general

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Design of Discrete-time Chaos-Based Systems for Hardware Security Applications

Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices

A survey of new technology for cockpit application to 1990's transport aircraft simulators

Two problems were investigated: inter-equipment data transfer, both on board the aircraft and between air and ground; and crew equipment communication via the cockpit displays and controls. Inter-equipment data transfer is discussed in terms of data bus and data link requirements. Crew equipment communication is discussed regarding the availability of CRT display systems for use in research simulators to represent flat panel displays of the future, and of software controllable touch panels

A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called post-processing. In this paper the hash function SHA-256 as post-processing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies