2,653 research outputs found
Continuous-time cascaded ÎŁÎ modulators for VDSL: A comparative study
This paper describes new cascaded continuous-time ÎŁÎ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely, transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.Ministerio de EducaciĂłn y Ciencia TEC2004-01752/MI
A design tool for high-resolution high-frequency cascade continuous- time ÎŁâ modulators
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran
Canaria, SpainThis paper introduces a CAD methodology to assist the de
signer in the implementation of continuous-time (CT) cas-
cade
ÎŁâ
modulators. The salient features of this methodology ar
e: (a) flexible behavioral modeling for optimum accuracy-
efficiency trade-offs at different stages of the top-down
synthesis process; (b) direct synthesis in the continuous-time
domain for minimum circuit complexity and sensitivity; a
nd (c) mixed knowledge-based and optimization-based architec-
tural exploration and specification transmission for enhanced
circuit performance. The applicability of this methodology
will be illustrated via the design of a 12 bit 20 MHz CT
ÎŁâ
modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y EducaciĂłn TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec
Adaptive design of delta sigma modulators
In this thesis, a genetic algorithm based on differential evolution (DE) is used to generate delta sigma modulator (DSM) noise transfer functions (NTFs). These NTFs outperform those generated by an iterative approach described by Schreier and implemented in the delsig Matlab toolbox. Several lowpass and bandpass DSMs, as well as DSM\u27s designed specifically for and very low intermediate frequency (VLIF) receivers are designed using the algorithm developed in this thesis and compared to designs made using the delsig toolbox. The NTFs designed using the DE algorithm always have a higher dynamic range and signal to noise ratio than those designed using the delsig toolbox
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 ÎŒm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e InnovaciĂłn TEC2009-08447Junta de AndalucĂa TIC-0281
Contribución al modelado y diseño de moduladores sigma-delta en tiempo continuo de baja relación de sobremuestreo y bajo consumo de potencia
Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-”m CMOS technology and it has a measured peak SNR of 62.5dB
Design and implementation of a wideband sigma delta ADC
Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTÆ©âM), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications.
The objective of this thesis is to design and implement a wideband CTÆ©âM for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTÆ©âM, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADCâs sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB.
This thesis focuses on the design and implementation of the CTÆ©âM, building upon the principles of a discrete time Æ©â modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTÆ©â modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTÆ©â modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTÆ©âM.
The CTÆ©âMs employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulatorâs performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. TiivistelmĂ€. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistĂ€ tĂ€rkeĂ€mmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnĂ€n kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTÆ©âM), joissa kĂ€ytetÀÀn ylinĂ€ytteistystĂ€ ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun.
TĂ€mĂ€n työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjĂ€rjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTÆ©âM, jolla on 15MHz:n signaalikaistanleveys. YlinĂ€ytteistyssuhde on 25 ja AD muuntimen nĂ€ytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR).
TĂ€mĂ€ työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Æ©â-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmĂ€ esitetÀÀn yksityiskohtaisesti, ja vaatimusten tĂ€yttyminen varmistetaan âtop-downâ -suunnitteluperiaatteella. LiitteenĂ€ on kertoimien laskemiseen kĂ€ytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkĂ€n silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentĂ€ -DA muunninta. Viivekompensointipolkua kĂ€yttĂ€mĂ€llĂ€ modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. LisĂ€ksi FIR takaisinkytkentĂ€ -DA-muuntimen kĂ€yttö pienentÀÀ kellojitteriherkkyyttĂ€, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyĂ€ ja luotettavuutta.
Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty perÀkkÀin integraattoreita myötÀkytkentÀrakenteella (CIFF) ja toisessa sekÀ myötÀ- ettÀ takaisinkytkentÀrakenteella (CIFF-B). PÀÀhuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa kÀyttÀen 0.8 voltin kÀyttöjÀnnitettÀ. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. LisÀksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin
Carbon footprint of 3D-printed bone tissue engineering scaffolds: an life cycle assessment study
The bone tissue engineering scaffolds is one of the
methods for repairing bone defects caused by various factors.
According to modern tissue engineering technology,
three-dimensional (3D) printing technology for bone tissue
engineering provides a temporary basis for the creation of
biological replacements. Through the generated 3D bone tissue
engineering scaffolds from previous studies, the assessment to
evaluate the environmental impact has shown less attention in
research. Therefore, this paper is aimed to propose the Model of
life cycle assessment (LCA) for 3D bone tissue engineering
scaffolds of 3D gel-printing technology and presented the
analysis technique of LCA from cradle-to-gate for assessing the
environmental impacts of carbon footprint. Acrylamide
(C3H5NO), citric acid (C6H8O7), N,N-Dimethylaminopropyl
acrylamide (C8H16N2O), deionized water (H2O), and
2-Hydroxyethyl acrylate (C5H8O3) was selected as the material
resources. Meanwhile, the 3D gel-printing technology was used
as the manufacturing processes in the system boundary. The
analysis is based on the LCA Model through the application of
GaBi software. The environmental impact was assessed in the
3D gel-printing technology and it was obtained that the system
shows the environmental impact of global warming potential
(GWP). All of the emissions contributed to GWP have been
identified such as emissions to air, freshwater, seawater, and
industrial soil. The aggregation of GWP result in the stage of
manufacturing process for input and output data contributed
47.6% and 32.5% respectively. Hence, the data analysis of the
results is expected to use for improving the performance at the
material and manufacturing process of the product life cycle
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