Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-µm CMOS technology and it has a measured peak SNR of 62.5dB

Patón Álvarez, Susana

English

Los moduladores Sigma-Delta de tiempo continuo constituyen una técnica de conversión de señal analógica a señal digital que resulta ser una alternativa interesante para aplicaciones de alta velocidad. Comparado con otras alternativas, son especialmente insensibles a las imperfecciones del circuito y a las tolerancias de los componentes, pero tradicionalmente se han diseñado para aplicaciones de baja-media velocidad. 
Esta tesis aporta contribuciones al análisis y modelado de moduladores Sigma-Delta en tiempo continuo y de alta velocidad. Se han analizado y modelado, entre otros, los dos efectos que limitan su resolución y estabilidad, a saber, el retardo de bucle en exceso y la sensibilidad del sistema a la incertidumbre del instante de muestreo. 
Los resultados del análisis así como los modelos obtenidos se han usado para proponer una metodología de diseño, novel y estructurada, que es válida para moduladores Sigma-delta en tiempo continuo de alta velocidad o baja relación de sobremuestreo. Para facilitar la evaluación de esta metodología se ha desarrollado una herramienta software que implementa las fases centrales de diseño. 
Finalmente, se ha validado la metodología de diseño propuesta mediante el desarrollo de un circuito integrado CMOS de 0.13 micras que implementa un modulador Sigma-Delta en tiempo continuo de 30 Megabits por segundo y 11 bits de rango dinámico.________________________________________________

Abstract Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-µm CMOS technology and it has a measured peak SNR of 62.5dB

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