Bruun, Erik

Nielsen, Jannik Hammel

In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient configuration of a CT single-loop ΣΔ ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 μm CMOS technology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63dB, consistent with 10 bits performance. Expected power consumption for the prototype is approx. 170 μW

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Downloaded from orbit.dtu.dk on: Dec 17, 2017A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/DConvertersNielsen, Jannik Hammel; Bruun, ErikPublished in:Proceedings IEEE International Symposium on Circuits and SystemsPublication date:2003Document VersionPublisher's PDF, also known as Version of recordLink back to DTU OrbitCitation (APA):Nielsen, J. H., & Bruun, E. (2003). A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/DConverters. In Proceedings IEEE International Symposium on Circuits and Systems (pp. 1069-1072). IEEE.A DESIGN METHODOLOGY FOR POWER-EFFICIENT CONTINUOUS-TIME EA AID CONVERTERS Jannik Hammel Nielsen and Erik Bruun BrstedaDTU, Technical University of Denmark DK-2800 Kgs. Lyngby, Denmark jhn@oersted.dtu.dk ABSTRACT In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) C A  AID converten. A method for performance prediction for EA A D  conveners is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient config- uration of a CT single-loop E A  ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 pm CMOS tech- nology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63 dB, consistent with 10 bits performance. Ex- pected power consumption for the prototype is approx. 170 pW. 1. INTRODUCTION Todays trend toward high ponability of everyday electronic de- vices ranging from telecommunication to biomedical devices. con- stitutes a major design challenge. The need for high durability of battery-powered devices coupled with ever-increasing perfor- mance requirements only enhances the need for low-power soh-  tians. Another factor is the decreasing voltage supply driven by technology scaling. This is due to the fact that low-voltage oper- ation of analog circuits requires high power consumption in order to retain sufficient dynamic range. An imponant building block in many devices is the A/D con- vener (ADC). Of the many possible variations of ADC topologies, the CA-modulator type remains highly interesting. This topol- ogy offers an elegant way to obtain high resolution for low- to moderate input frequencies and yet still maintain modest require- ments for the analog building blocks. In the past decade, this ADC topology has shown it's robustness through many implementations using the discrete-time (DT) switched-capacitor (SC) technique. However as supply voltages decrease with technology scaling, the SC technique is becoming less viable. CT implementations holds promise of lower power consump- tion and are less dependent on supply scaling than their DT coun- terparts. The price paid is increased sensitivity towards e.g. clock jitter and other non-idealities. 2. CT EA-MODLKATORS Employing a CT loop-filter for the EA ADC realisation holds several advantages. As the sampler is located deep in the loop, implicit anti-aliasing (AA) is native to the CT EA ADC, often This work was supported by the Danish Medical Research Council t . Figure I :  Continuous-Time EA-modulator. (a) DT Feedback Filter (b) CT Feedback Piltcr Figure 2: Feedback filters in DT and CT modulators. making an explicit AA-prefilter redundant. The necessary gain- bandwidth (GBW) of the integrators is typically a factor of 3 lower than their DT counterparts [2] for a given sampling frequency fa.  These properties imply that a significantly lower power con- sumption can be achieved by using B CT loop-filter over the DT counterpart. A single-loop CT EA ADC of order N is shown in fig. I. This configuration is well suited for low-power as only the first integra- tor has stringent requirements imposed on it. This is due to the filtering from all other internal nodes to the ou~put. The quantizer is sampled at f. from which we can define the oversampling ratio: OSR = f*/Zfb,  where f b  is the baseband frequency. 2.1. DT to CT Mapping In order to be able to obtain fast and yet precise simulation of the CT ADC performance. a DT/CT equivalence can be established. This also allows us to use the design methods usually employed for DT C A  ADCs. In fig. 2, a linear model of the ADC is shown from a loopfilter perspective in both a DT and CT version. The 1-1069 0-7803-7761-310311617.00 02003 JEEE Authorized licensed use limited to: Danmarks Tekniske Informationscenter. Downloaded on February 24,2010 at 04:29:02 EST from IEEE Xplore.  Restrictions apply. Table I : Mapping of DT to CT filter coefficients. signal transfer function (STF) and noise transfer function (NTF) for fig. 2(a) are respectively: (1) 1 1 + K H ( z )  STF( r )  = K H ( z )  z 1, NTF(z)  = 1 + K H ( z )  An often used approach for the design of EA-modulators is to choose a desired NTF (e.g. buttenvonh etc.) [I]. From the NTF, the feedback filter H ( z )  can be derived, determining the feedback coefficients. Since the CT modulator in fact constitutes a sam- pled system, a CT feedback filter equivalent to the DT filter can be obtained by requiring that the outputs are equal at the sampling instant. Referring to fig. 2, we thus have that: A H ( z )  = z { H ( s ) G ~ ~ d s ) }  = H ( x )  (2) where H ( s ) G o ~ d s )  = H ( s ) ,  constitutes the combined feed- back filter. Assuming a zero-order-hold feedback DAC with a NRZ feedback waveform, the s-domain transfer function of the DAC is: Goads) = [l - exp FsT)] /S. Forasingle-loop mod- ulator of order N, the CT and DT feedback filters can be written respectively: Taking the z-transform of each order of H ( s )  can be shown to be: where B,(x)  is a polynomial in z of order n. By comparing the coefficients of z in H ( z )  and H ( z ) ,  a set of linear equations result from which the mapping between the DT d-coefficients and the CT c-coefficients can be established. In table 1, the mapping for modulators of orders 2 through 4 is given. 2.2. Performance Prediction The quantizer in the E A  constitutes a highly nonlinear element. As shown in fig. 1, the quantizer can be modelled as a gain factor K ,  and an additive noise source q(n). I n  [I]  a quasilinear model of the 1-bit quantizer is proposed. If a signal with a sufficiently high amplitude is applied at the mod- ulator input, the modulator will become unstable. The maximum stable amplitude (MSA) can be shown to be a function of the feed- back filter cut-off frequency fc. Assuming a heavily oversampled input signal, the output power: a: = 1 - m,, can be attributed SQNR and MSA vs. Fm and OSR 1W 150 MO 258 FCut [W Figure 3: SQNR and MSA in a a 3'd order EA ADC vs. fc for increasing OSR. solely IO the quantization noised,. Hence we can define a noise amplification factor, A ( K )  [I]: where Parseval's theorem has been used to obtain the time-domain representation. my is the mean of the modulator output. Due to the high feedback filter gain, we have that m, = my. As the quantization noise is in fact not an independent signal source, but generated by the input signal itself, we can estimate a: from m, and the quantizer input probability density function (PDF) [I]. For higher order modulators ( N X 2 ) .  the quantizer input is well approximated by a gaussian PDF. For a gaussian PDF, we have 141: a' - 1 - mz - - 2 exp [-2 (erf-' (m,))'] (6) y f f  q -  where erf-', is the inverse error function. As the lowest amount of quantization noise is attained at the MSA, the minimum value of A ( K )  yields the MSA. Hence by combining eq. (5-6) we can obtain an estimate of the MSA . However, as A ( K )  is an increasing function of the NTF cut- off frequency [I]. the MSA is inverserly proponiond to fc and hence a trade-off exists between a high fc, i.e. high quantization noise supression, and a high MSA, i.e. high signal power. Due to the intrinsic minimization of the quantization noise. an equilibrium quantizer ain Keq, can be estimated by the K which minimizes IlntfK1lz / K z .  The obtained K., determines both NTFK(z)  and A ( K ) .  From eq. ( 5 ) .  the quantization noise for zero input can be found: a: = I / A ( K a q ) .  For a base-band frequency of fb. the signal to quantization-noise ratio (SQNR) for a sinusoid at MSA can be estimated: B In fig. 3 the predicted MSA and SQNR for a third order E A  is shown vs. f c  for different OSRs. The abrupt drop-off of the SQNR 1-1070 Authorized licensed use limited to: Danmarks Tekniske Informationscenter. Downloaded on February 24,2010 at 04:29:02 EST from IEEE Xplore.  Restrictions apply. Power V I .  OSR and Fc, Figure 4 FIR2 combfilter structure. curves occur as the MSA approaches zero. From fig. 3, it is seen that the maximum SQNR is obtained at a MSA of approx. 0.3. This low value is due to the fact that the noise suppression grows "faster" for increasing fc than the MSA decreases. 2.3. Decimation filter A popular choice for decimation filters is  the combfilter which can be implemented without using computationally expensive multi- pliers. The combfilter transfer function is given by I31: where D is thz decimation factor and k is the order of the filter. The second form of eq. (8) can be implemented by a series of FIR filters each decimating by a factor of two as shown in fig. 4. The wordlength of the registers at the ouput of each FIR stage is equal to (WO + hi )  bits, where WO is the number bits at the filter input. Hence we have a filter configuration where the full sampling frequency is only applied to the first stage, which only has a wordlength of a few bits. Whereas the other stages. with increasing wordlength, arc clocked at decimated frequencies giv- ing B power-efficient decimation filter [3]. For a EA-modulator of order N. a decimation filter of order N+I suffices for out-of-band q~ant iza t ton  noise suppression. 3. CT CA-MODULATOR OPTIMIZATION As was previously seen. the MSA is invcrsely proportional to the fecdback filter cut-off frequency. Howeverthe SQNR curves sug- ~ C S ~ E  that the maximum SQNR is  achieved for low values of the MSA. A very low MSA points towards a very high power con- sumption in the analog Implementation. since in order to obtain thc desired dynamic range, vcry low noise analog blocks must be developed. indicating high biasing currents. Clearly. a wade-off exists between the analog power consump- t m .  the MSA and the SQNR. 3.1. Power estimation The core elements of an analog integrator consists of an integrating capacitor and a regulating active element. e.g. an op-amp. The power consumption 01 the active element is then determined by ihc CBW ncccssiliited by the integrator specifications, e.&. max. input frequency. Whereas the size of the capacitor is determined by noise limitations hereby sctting dynamic power consumption. We have prcviously derived an expression for the quantization n o m  0:. Refcrring the quantization mix 10 a referencc voltage %,I and taking the combined filtering of NTF(z) and Hco,,, b(z) into account. we have thc resulting quantization noise power: '-, -1 5c.m Figure 5 :  Inverse power consumption of a Jd order E A  ADC. The thermal noise accumulated on the integrating capacitor is: NEF . kT PTh = ~ Ci", where NEF is the Noise Excess Factor taking the added circuitry noise into account. The total amount of noise allowable for a resolution of b bits is given by: Combining equations (9-1 I), we can solve forthe minimum allow- able capacitor size: The static power consumption is  determined by the required GBW of the regulating cell. A first order approximation of the necessary bias current l e ,  can be found CI is the loading capacitance and B is the beta of the driving MOS transistor. As the output of the first integrator goes unattenuated to the ADC output. the requirements of this block are as strict as fnr the overall system. The outputs of the other blocks however, are filtered and the requirements for these can hence be significantly loosened. The CBW of the integrators can be lessened, implying a lower I g  and !more noise can be tolerated on the integrating ca- pacitors, allowing fur a smaller capacitors Ci",. Let Pc denote the quantizer power per frequency, the analog powcr is then approximated by: i = ,  i=, m is the number of current branches in the regulating element and the summations indicate the scaling of bias currents and capacitors for the cascade of integrators. 1-1071 Authorized licensed use limited to: Danmarks Tekniske Informationscenter. Downloaded on February 24,2010 at 04:29:02 EST from IEEE Xplore.  Restrictions apply. Power Consumption Supply Voltage Sampling Frequency 1.5 MHz. (OSR=75) Feedback filter cut-off frequency, fc > 6 5 d B  SFDR > 6 3 d B  Technology 0.35 p m  CMOS I I 171 UW I 100 kHz “.&. , ““U- I I 5  Table 2: Test design performance summary The digital circuitry when using the FIR2 decimation filter structure is confined to D-flip flops, half- and fulladders. For a given clock frequency we have: log. D - l  fclk P d i g  = U (pta + P h a  + Pdff) (15) i= l  The frequency dependent power consumption of the digital blocks can be found in the datasheets of the employed technology. a de- notes the activity factor. The total power of the modulator is thus given by: PW = Pan + Pd;g .  The inverse power is plotted for a third order modulator in fig. 5, where 10 bits of accuracy is required and V,,i = 200 mV. A clear peak is observed, indicat- ing that a global optimum with regards to power efficiency exists. Hence an optimum fCw and f c  can be extracted for a modulator of order N .  4. TESTCASE In order to verify the developed design method. a prototype ADC requiring 10 bits performance was simulated. In the table below, the projected power consumption of EA ADCs of order 2-5 are shown. indicating that a third order EA is suitable for the specifi- cations. N I  2 / 3 1 4 1 5  P[pW] I 308 I 164 1 195 I 257 The prototype EA ADC was simulated at transistor level us- ing a 0.35 pm CMOS process. The integrators were implemented as G, - C cells, where the G, was obtained by placing a MOST in the linear region and the nccessary GBW given by the speed re- quirements for the regulating loop. An example output spectrum with a tone at the MSA of the prototype modulator is shown in fig. 6. The third harmonic i s  below -63 dB, indicating 10 bits spurious-free performance is obtained. The fifth harmonic is not visible as it is buried beneath the noise floor. The even order har- monics are suppressed due to the fully differentialstructure. Over- laid the spectrum, the employed decimating comb-filter transfer function is shown. A summary of the prototype CA-modulator performance is given in table 2. A comparison with an equivalent SC EA ADC is in it’s place. The number of time constants n, necessary for first order settling behaviour to b bits can be found from: n > (6  + 1) In (2). which resolves to n I 8 for 10 bits performance. Using a first order model of an op-amp, we have that: GBW = gm/Cint = lis, where the transconductance is: gm = m. Requiring the out- put to settle within half a clock-period, we have that: l / r  = 16f,. Hence we can approximate the necessary bias current: (16) (16fSCi,t)’ 24 IB = Figure 6 Output spectrum of the test design EA ADC. Using the same capacitor sizes and parameters as in the prototype ADC and employing a folded cascode op-amp, the static power consumption of the integrators can be found to be: P,,.,,DT I 335 p W .  Whereas the corresponding CT consumption in the pro- totype ADC is: p,,,,,,~ I^ 111 pW. Hence an estimated 2/3 of the static integrator power consumption has been saved by em- ploying a CT structure. S. CONCLUSION A design methodology for CT single-loop EA ADCs has been presented in this paper. The theory necessary for performance prediction was shown and a method for estimation of power con- sumption. For a given set of specificatons. the theory allows an optimum Z A  order. feedback filter cut-off frequency and sam- pling frequency to be extracted. Finally, a test case was speci- fied and optimized in order to verify the theory The prototype has performance in good correspondance with the expected results from the optimization routine. verifying the validity of the pro- posed methodology. An estimate of the power consumption of an equivalent DT cascade of integrators showed that power savings of approx. 2/3 had been obtained by using the CT configuration. 6. REFERENCES [ I ]  L. Risba, “Stability Predictions for High-Order C - A Mad- ulators Based on Quasilinear Modeling”. Proc. ISCAS ‘94, May-Jun. 1994, Vol. 5,  pp. 361-364. [2] F. Gerfers, Y. Manoli, “A 1.5V Low-Power Third Order Continuous-Time Lowpass CA A D  Convener ’*. Proc. ofrhe Inr. Symposium on Low Power Elecrronics and Design,-Jun. 2000, pp. 219-221. [3] Aboushady, et. al., “Efficient Polyphase Decomposition of Comb Decimation Filters in EA Analog-to-Digital Conven- ers”. IEEE Trans. Circuits and Sysr. 11. vol. 48, pp. 898-903. Oct.,  2001. [4] S.  H. Ardalan and J .  1. Paulos, “An analysis of nonlinear be- haviour in delta-sigma modulators”. IEEE Trans. Circuirs and Sysr., vol. 34, pp. 593-603, Jun. 1987. 1-1072 Authorized licensed use limited to: Danmarks Tekniske Informationscenter. Downloaded on February 24,2010 at 04:29:02 EST from IEEE Xplore.  Restrictions apply. 

A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters

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A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters

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