縦型ボディチャネルMOS Field-Effect Transistorを用いたマイクロプロセッサ向け高効率・高集積DC-DCコンバータとそのパワーマネジメントに関する研究

Tohoku University遠藤哲郎課

Skybridge: A New Nanoscale 3-D Computing Framework for Future Integrated Circuits

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We propose a new 3-D IC fabric technology, Skybridge [6], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge’s core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance/watt benefits, and 10x reduction in interconnect lengths vs. scaled 16-nm CMOS [6]. Fabric-level heat extraction features are found to be effective in managing IC thermal profiles in 3-D. This 3-D integrated fabric proposal overcomes the current impasse of CMOS in a manner that can be immediately adopted, and offers unique solution to continue technology scaling in the 21st century

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.Comment: 53 Page

Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Vertical III-V Nanowires For In-Memory Computing

In recent times, deep neural networks (DNNs) have demonstrated great potential in various machine learning applications,such as image classification and object detection for autonomous driving. However, increasing the accuracy of DNNsrequires scaled, faster, and more energy-efficient hardware, which is limited by the von Neumann architecture whereseparate memory and computing units lead to a bottleneck in performance. A promising solution to address the vonNeumann bottleneck is in-memory computing, which can be achieved by integrating non-volatile memory cells such asRRAMs into dense crossbar arrays. On the hardware side, the 1-transistor-1-resistor (1T1R) configuration has been centralto numerous demonstrations of reservoir, in-memory and neuromorphic computing.In this thesis, to achieve a 1T1R cell with a minimal footprint of 4F2, a technology platform has been developed to integrate avertical nanowire GAA MOSFET as a selector device for the RRAM. Firstly, the effect of the geometry (planar to vertical) ofthe ITO/HfO2/TiN RRAM cell was studied where low energy switching (0.49 pJ) and high endurance (106) were achievedin the vertical configuration. Furthermore, InAs was incorporated as the GAA MOSFET selector channel material toleverage the beneficial transport properties of III-V materials desirable for supply voltage scaling. Finally, an approach wasdeveloped wherein InAs is used as the selector channel as well as the RRAM electrode by carefully tuning the InAs nativeoxides. This thesis also presents low-frequency noise characterization of the RRAM cell as well as the MOSFET to furtherunderstand the semiconductor/oxide interface. The vertical 1T1R cell developed in this thesis enables the implementationof Boolean logic operations using a single vertical nanowire while reducing the footprint by 51x when compared to itstraditional CMOS counterpart

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Department of PhysicsSubthreshold swing is one of most important parameters in controversial metal-oxide-semiconductor (CMOS) technology, which is related on power consumption. In the metal-oxide-semiconductor field effect transistor (MOSFET), there is thermodynamic limit of subthreshold swing of 60 mV/dec at room temperature. In order to achieve the subthreshold swing, edge-over MOSFET structure is proposed, transistor channel of EO MOSFET is formed on sidewall of insulating pillar. Therefore, transistor channel length increases even though the lateral transistor channel length is maintained. Since the subthreshold swing is deteriorated by the short channel effect, relatively long channel due to existence of insulating pillar has advantage to suppress the subthreshold swing in nano-meter scale. By technology computer aided design (TCAD) modeling, electrical characteristics are demonstrated. Low drain induced barrier lowering (DIBL) of 13.7 mV/V and steep subthreshold swing of 62.6 mV/dec are estimated. Ternary characteristics of EO ternary inverter are investigated by TCAD Mixed mode, the voltage transfer characteristics (VTC) of EO ternary inverter gives an apparent ternary voltage states. In according to structures of EO resistor and EO MOSFET, EO ternary inverter can be formed perpendicular to substrate, therefore, which allows thin lateral dimension of the inverter. Reliability of ternary operation is explained with static noise margin (SNM) and transient response. In the transient response, ternary operation is maintained at 10 MHz frequency, and a propagation delay of 1.69 ns is evaluated. Theoretical approach to thermionic emission at Dirac semimetal source is performed. In the Dirac semimetal, since density of states are determined by linear energy dispersion near the Dirac point, thermionic emission current can be controlled by difference between Dirac point and fermi level and Schottky barrier height. As absence of direct injection of carriers from contact to Si, equation of thermionic emission is different with that of conventional up-down source/substrate structure. In case of graphene, there are singularities at negative infinity, hence the possibility of constant thermionic current exists regardless of the gate biasing of MOSFET. Meanwhile, lowest subthreshold swing of 30 mV/dec for 3 dimensional Dirac semimetal source is discussed.clos